| To: | linux@cthulhu.engr.sgi.com |
|---|---|
| Subject: | Magnum 4000 caches |
| From: | Ralf Baechle <ralf@mailhost.uni-koblenz.de> |
| Date: | Thu, 23 Oct 1997 19:05:10 +0200 (MEST) |
| Sender: | owner-linux@cthulhu.engr.sgi.com |
Hi, maybe one of the old Mips people can answer me two questions: - why do the Magnum 4000PC instruction and data caches have a different linesize for the L1 caches, but the Magnum 4000SC not? - does the Magnum 4000SC use a split instruction/data L2 cache? TIA, Ralf |
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