Can anybody give me a pointer to where the R5000 caches, especially
the cache instruction, are documented? My two IDT R5000 manuals don't
contain the least bit of information regarding the cache instruction.
I'm primarily interested in how the indexed operations select the
cache set of the primary caches to operate on. On the R4600 which has
16kb per cache bit 13 selects the set. So I assume it's bit 14 on the
R5000 with it's 32kb per cache? The code from David handles the
R5000 like a R4000 CPU but this doesn't look very credible to me as
this is a QED CPU and the other members of the R5k family like the
Nevada (which run Linux now also!) have two way primary caches.