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Re: clock skew and ethernet timeouts

To: linux@fir.engr.sgi.com
Subject: Re: clock skew and ethernet timeouts
From: "William J. Earl" <wje@fir.engr.sgi.com>
Date: Mon, 18 Aug 1997 16:34:36 -0700
In-reply-to: <199708142315.BAA06429@informatik.uni-koblenz.de>
References: <199708132209.RAA31518@speedy.rd.qms.com> <199708142315.BAA06429@informatik.uni-koblenz.de>
Sender: owner-linux@cthulhu.engr.sgi.com
Ralf Baechle writes:
...
 > There are more thing which need to be reworked with resprect to interrupts.
 > For example cache flushing turns interrupts off for sometimes several
 > thousand cycles even though this is only required for certain buggy CPUs
 > like the R4600 v1.x.  And even there are better workarounds.  General
 > rule about cli():  Think about it if you really need it.  Then think again
 > about it.  If you're finished wnd still think cli() might be a good solution,
 > then think once again about it ...
...

     In IRIX, I had the cache flushing code, when doing writebacks on
the R4600 and the like, reenable interrupts every page, to limit the
wait time (to about 50 us. on an Indy).  I patched out the extra instructions
to disable and reenable interrupts on processors which did not require them.
Assuming that the code uses index invalidate or index writeback invalidate
when the buffer is larger than the cache, the invalidate-only case (without
writeback) is short enough (5 us. or less) that reenabling interrupts is
not needed.  The writeback case takes much longer, in the worst case,
because each cache line must be written to memory, taking about 400 ns.
each on the Indy.


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