| To: | ralf@mailhost.uni-koblenz.de |
|---|---|
| Subject: | Re: Modules |
| From: | "David S. Miller" <davem@jenolan.rutgers.edu> |
| Date: | Sat, 26 Jul 1997 13:41:29 -0400 |
| Cc: | linux@cthulhu.engr.sgi.com |
| In-reply-to: | <199707261726.TAA00825@informatik.uni-koblenz.de> (message from Ralf Baechle on Sat, 26 Jul 1997 19:26:55 +0200 (MET DST)) |
| Sender: | owner-linux@cthulhu.engr.sgi.com |
From: Ralf Baechle <ralf@mailhost.uni-koblenz.de> Date: Sat, 26 Jul 1997 19:26:55 +0200 (MET DST) Right now I really wonder why modules work at all on any architecture with split I/D caches. On most sparc32's with split I/D, the Icache fully snoops the L2 and even the store buffer. On sparc64, I flush the icache when a module mapping is made... |
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