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R4k taglo/taghi hardware bugs^H^H^H^Hfeatures?

To: linux@cthulhu.engr.sgi.com
Subject: R4k taglo/taghi hardware bugs^H^H^H^Hfeatures?
From: "David S. Miller" <dm@neteng.engr.sgi.com>
Date: Mon, 24 Jun 1996 05:25:17 -0700
Reply-to: dm@sgi.com
Sender: owner-linux@cthulhu.engr.sgi.com
Are there any known problems with the taglo/taghi registers showing
what they should after "indexed load tag secondary" cache
instructions?  Whatever is in both registers before the cache
instruction, is still in there afterwards...  I've also tried the
primary-data and primary-instruction variants of the cache operations
and still same results.

I don't know, but it is so nice how the primary cache sizes are stored
in well defined config registers in CP0, yet the secondary cache needs
to be sized by complete magic and diagnostic mechanisms.  The CPU
knows the size of the secondary cache lines, why so difficult to put
the secondary cache total size somewhere similar?  (for those of you
playing at home, yes I know the R5k Triton does this in the CP0 config
register, but all other R4k variants do not)

I've been up all night trying to figure out what (isn't) happening...

Later,
David S. Miller
dm@sgi.com

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