mtc0/eret hazard for the R4600, R4700, and R5000

[wje@fir.esd.sgi.com (William J. Earl)]

     We recently noticed an error in the CP0 hazard table for the above
processors.  Specifically, the eret row in the table in Appendix F is
incorrect.  There must be two instructions between an mtc0 which changes
a register read by eret and an eret, not just one.  This is not normally
a problem, but it does mean that one must keep the mtc0 which restores $epc
far enough away from the eret.