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Re: [patch] MIPS64 R4k TLB refill CP0 hazards

To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Wed, 31 Jul 2002 00:47:02 +0200
Cc: Carsten Langgaard <carstenl@mips.com>, linux-mips@fnet.fr, linux-mips@oss.sgi.com
In-reply-to: <Pine.GSO.3.96.1020730141305.16647B-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Tue, Jul 30, 2002 at 02:44:32PM +0200
References: <3D4681DE.7BE793C9@mips.com> <Pine.GSO.3.96.1020730141305.16647B-100000@delta.ds2.pg.gda.pl>
User-agent: Mutt/1.2.5.1i
On Tue, Jul 30, 2002 at 02:44:32PM +0200, Maciej W. Rozycki wrote:

>  Since the handler is critical for performance, it would be desireable to
> have separate versions tuned for particular CPUs.  The branch for the
> R4400 seems appropriate as it works unlike the documented code: the
> R4000/R4400 manual as available from the MIPS site states a single
> intervening instruction is needed before the last move to EntryLo and a
> "tlbwr" or "tlbwi" (see Table F-1 and F-2).  So I conclude the branch is
> really a workaround for a kind of erratum or a specification change. 

Nope, on R4000 four cycles are needed between the tlbwr and a eret
instruction; on the R4600 just two.

  Ralf

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