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[patch] linux: Cache coherency fixes

To: Ralf Baechle <ralf@uni-koblenz.de>
Subject: [patch] linux: Cache coherency fixes
From: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Date: Fri, 5 Jul 2002 17:21:34 +0200 (MET DST)
Cc: linux-mips@fnet.fr, linux-mips@oss.sgi.com
Organization: Technical University of Gdansk
Ralf,

 Following is a fix for the currently broken TLB cache coherency
attributes setup.  Of R4[04]00 processors only the MC versions support
cache coherency.  Looking at the current setup I infer SB1 is another CPU
that supports it -- for any other CPU, the patch will have to be updated.
Then it's only relevant for SMP setups. 

 My R4400SC locks up solid (and I mean it, even NMI doesn't work) when a
write back of a line marked as CACHABLE_COW is to happen.  Somebody's
laziness costed me a week of debugging, sigh... :-(

 OK to apply?

  Maciej

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +

patch-mips-2.4.19-rc1-20020705-cache-coherency-2
diff -up --recursive --new-file 
linux-mips-2.4.19-rc1-20020705.macro/arch/mips/config.in 
linux-mips-2.4.19-rc1-20020705/arch/mips/config.in
--- linux-mips-2.4.19-rc1-20020705.macro/arch/mips/config.in    2002-06-27 
02:57:13.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020705/arch/mips/config.in  2002-07-05 
14:58:52.000000000 +0000
@@ -393,6 +393,19 @@ else
       fi
    fi
 fi
+
+if [ "$CONFIG_CPU_R4X00" = "y" -o "$CONFIG_CPU_SB1" = "y" ]; then
+   define_bool CONFIG_CPU_CACHE_COHERENCY $CONFIG_SMP
+else
+   define_bool CONFIG_CPU_CACHE_COHERENCY n
+fi
+
+if [ "$CONFIG_VTAG_ICACHE" != "y" ]; then
+   define_bool CONFIG_VTAG_ICACHE n
+fi
+if [ "$CONFIG_CPU_HAS_PREFETCH" != "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH n
+fi
 endmenu
 
 mainmenu_option next_comment
diff -up --recursive --new-file 
linux-mips-2.4.19-rc1-20020705.macro/arch/mips64/config.in 
linux-mips-2.4.19-rc1-20020705/arch/mips64/config.in
--- linux-mips-2.4.19-rc1-20020705.macro/arch/mips64/config.in  2002-06-27 
02:57:26.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020705/arch/mips64/config.in        2002-07-05 
14:59:16.000000000 +0000
@@ -126,7 +126,6 @@ choice 'CPU type' \
         R8000  CONFIG_CPU_R8000 \
         R10000 CONFIG_CPU_R10000 \
         SB1    CONFIG_CPU_SB1" R4x00
-endmenu
 
 if [ "$CONFIG_CPU_SB1" = "y" ]; then
    bool '  Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
@@ -137,6 +136,20 @@ fi
 define_bool CONFIG_CPU_HAS_LLSC y
 define_bool CONFIG_CPU_HAS_LLDSCD y
 
+if [ "$CONFIG_CPU_R4X00" = "y" -o "$CONFIG_CPU_SB1" = "y" ]; then
+   define_bool CONFIG_CPU_CACHE_COHERENCY $CONFIG_SMP
+else
+   define_bool CONFIG_CPU_CACHE_COHERENCY n
+fi
+
+if [ "$CONFIG_VTAG_ICACHE" != "y" ]; then
+   define_bool CONFIG_VTAG_ICACHE n
+fi
+if [ "$CONFIG_CPU_HAS_PREFETCH" != "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH n
+fi
+endmenu
+
 mainmenu_option next_comment
 comment 'General setup'
 
diff -up --recursive --new-file 
linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips/pgtable-bits.h 
linux-mips-2.4.19-rc1-20020705/include/asm-mips/pgtable-bits.h
--- linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips/pgtable-bits.h        
2002-04-15 07:50:23.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020705/include/asm-mips/pgtable-bits.h      
2002-07-05 14:52:59.000000000 +0000
@@ -74,9 +74,9 @@
 #define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
 #define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
 #define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
-#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00 only           */
-#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00 only           */
-#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00 only           */
+#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00MC only         */
+#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00MC only         */
+#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00MC only         */
 #define _CACHE_UNCACHED_ACCELERATED (7<<9)  /* R10000 only             */
 
 #endif
@@ -87,12 +87,20 @@
 
 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | 
_CACHE_MASK)
 
-#ifdef CONFIG_MIPS_UNCACHED
+
+#if defined(CONFIG_MIPS_UNCACHED)
+
 #define PAGE_CACHABLE_DEFAULT  _CACHE_UNCACHED
-#elif CONFIG_CPU_SB1
+
+#elif defined(CONFIG_CPU_CACHE_COHERENCY)
+
 #define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_COW
+
 #else
+
 #define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_NONCOHERENT
+
 #endif
 
+
 #endif /* _ASM_CACHINGMODES_H */
diff -up --recursive --new-file 
linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips64/pgtable.h 
linux-mips-2.4.19-rc1-20020705/include/asm-mips64/pgtable.h
--- linux-mips-2.4.19-rc1-20020705.macro/include/asm-mips64/pgtable.h   
2002-07-03 02:58:29.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020705/include/asm-mips64/pgtable.h 2002-07-05 
14:52:59.000000000 +0000
@@ -191,9 +191,9 @@ extern void (*_flush_icache_page)(struct
 #define _CACHE_CACHABLE_WA          (1<<9)  /* R4600 only              */
 #define _CACHE_UNCACHED             (2<<9)  /* R4[0246]00              */
 #define _CACHE_CACHABLE_NONCOHERENT (3<<9)  /* R4[0246]00              */
-#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00 only           */
-#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00 only           */
-#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00 only           */
+#define _CACHE_CACHABLE_CE          (4<<9)  /* R4[04]00MC only         */
+#define _CACHE_CACHABLE_COW         (5<<9)  /* R4[04]00MC only         */
+#define _CACHE_CACHABLE_CUW         (6<<9)  /* R4[04]00MC only         */
 #define _CACHE_UNCACHED_ACCELERATED (7<<9)  /* R10000 only             */
 #define _CACHE_MASK                 (7<<9)
 
@@ -202,15 +202,21 @@ extern void (*_flush_icache_page)(struct
 
 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | 
_CACHE_MASK)
 
-#ifdef CONFIG_MIPS_UNCACHED
-#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
-#else /* ! UNCACHED */
-#ifdef CONFIG_SGI_IP22
-#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
-#else /* ! IP22 */
-#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
-#endif /* IP22 */
-#endif /* UNCACHED */
+
+#if defined(CONFIG_MIPS_UNCACHED)
+
+#define PAGE_CACHABLE_DEFAULT  _CACHE_UNCACHED
+
+#elif defined(CONFIG_CPU_CACHE_COHERENCY)
+
+#define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_COW
+
+#else
+
+#define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_NONCOHERENT
+
+#endif
+
 
 #define PAGE_NONE      __pgprot(_PAGE_PRESENT | PAGE_CACHABLE_DEFAULT)
 #define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \

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