| To: | Ralf Baechle <ralf@uni-koblenz.de> |
|---|---|
| Subject: | Re: I have question related for caches in R3000. |
| From: | Jun Sun <jsun@mvista.com> |
| Date: | Wed, 13 Jun 2001 11:22:15 -0700 |
| Cc: | "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, Shinkyu Kang <cosmos@astonlinux.com>, linux-mips@fnet.fr |
| References: | <20010612140551.A5285@bacchus.dhis.org> <Pine.GSO.3.96.1010613130609.9854F-100000@delta.ds2.pg.gda.pl> <20010613134746.A31758@bacchus.dhis.org> |
| Sender: | jsun@hermes.mvista.com |
Ralf Baechle wrote: > > On Wed, Jun 13, 2001 at 01:06:56PM +0200, Maciej W. Rozycki wrote: > > > > Your CPU is not one of those and therefore you'll have to make a few > > > changes to arch/mips/mm/r2300.c. > > > > A separate new file might be a better idea... > > Splitting all those files into TLB, cache and all the rest is long overdue > and if we keep supporting more and more hardware we'll still have to do it > in the 2.4 timeframe. > How soon will 2.5 come? Splitting TLB and cache support should not take too long - except it is indeed a big change in structure. Jun |
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