> Greeen-III wrote:
> Hi all,
> I am in the pthread problem.
> I guess the reason is context switch.
> So I trace the code /arch/mips/kernel/traps.c and
> I have some question want to ask you.
> 1. What condition the kernel will simulate the instruction "ll" and
> "sc"? (In the traps.c)
The Reserved Instruction exception is occured and fault intruction has
ll or sc opcode.
> 2. What is the functional of the variable "ll_bit" ? (In the traps.c)
The sc emulation codemust know by definition whether ll instruction has
been occured in the control sequence.
> 3. What situation does kernel call the resune ? (In the
On context switch, it's implementation of switch_to.
> 4. The traps.c is initialize IDT( interrupt descripter table ), Right?