I am in the pthread problem.
I guess the reason is context switch.
So I trace the code /arch/mips/kernel/traps.c and
I have some question want to ask you.
1. What condition the kernel will simulate the instruction
"ll" and "sc"? (In the traps.c)
2. What is the functional of the variable "ll_bit" ? (In the traps.c)
3. What situation does kernel call the resune ? (In the
4. The traps.c is initialize IDT( interrupt descripter
table ), Right?