First of all, your solution is unfortunately 5 instructions and not 4 - the
assembler will put a NOP after the 'beq' instruction to fill the branch delay
slot - otherwise the 'sub' instruction will be executed anyway.
However, there is a 3 instruction sequence to do the job (actually there are a
few different variations) assuming your MIPS is ISA level II or above:
sub $t2, zero, $t3
bgezl $t3, OUT
add $t2, zero, $t3
Hope that helps....
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