| To: | Jun Sun <jsun@mvista.com> |
|---|---|
| Subject: | Re: PROPOSAL : multi-way cache support in Linux/MIPS |
| From: | Ralf Baechle <ralf@oss.sgi.com> |
| Date: | Thu, 3 Aug 2000 01:31:55 +0200 |
| Cc: | "Kevin D. Kissell" <kevink@mips.com>, linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr |
| In-reply-to: | <3988AA72.5C342E1D@mvista.com>; from jsun@mvista.com on Wed, Aug 02, 2000 at 04:10:43PM -0700 |
| References: | <027f01bffcd3$3279b800$0deca8c0@Ulysses> <3988AA72.5C342E1D@mvista.com> |
On Wed, Aug 02, 2000 at 04:10:43PM -0700, Jun Sun wrote: > > So, to get back to Linux, a MIPS32 part can *almost* > > run the standard MIPS R4K kernel. Almost. What had > > Still one more question. If I understand correctly, the 4Km and 4Kp are > MIPS32 CPUs. However, they don't have TLBs. Right? Without TLBs, I > don't suppose Linux will run ... There is ``Microcontroller Linux'' aka uclinux available at www.uclinux.org. It could be ported to TLB-less processors. You'd loose some of the important functionality of the standard Linux, including some source compatibility. Ralf |
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