linux-mips-fnet
[Top] [All Lists]

Re: R5000 support (specifically two-way set-associative cache...)

To: Dominic Sweetman <dom@algor.co.uk>
Subject: Re: R5000 support (specifically two-way set-associative cache...)
From: Jun Sun <jsun@mvista.com>
Date: Fri, 30 Jun 2000 18:22:58 -0700
Cc: linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com, nigel@algor.co.uk
References: <394EA5A0.B882F66A@mvista.com> <200006200947.KAA08574@mudchute.algor.co.uk> <394FBAC6.3D29C4A7@mvista.com> <394FBF91.76AE6FD0@mvista.com> <200006202059.VAA19304@mudchute.algor.co.uk>
Sender: jsun@hermes.mvista.com
> Fundamentally:
> 
> o "index" operations just go first through one set, then the other.
>   So long as initialisation routines are applied to each possible
>   index in turn, both sets get initialised.
> 
> o "hit" operations "just work".
> 
> So long as initialisation is done carefully (basic rule: perform one
> stage to the whole cache before going on to the next), run-time cache
> maintenance can and should be done with "hit" instructions, and you
> don't need to worry whether the CPU is direct mapped, 2- or 4-way set
> associative.
> 
> (it's all explained in my book, "See MIPS Run", of course...)
> 
> Even with the Vr5432 you only have to know the difference when first
> setting up the CPU.
> 

Not exactly - the current Linux/MIPS implementation uese index
operations to flush cache.
As a result flush_all_cache() does not really flush all cache.


> Dominic Sweetman
> Algorithmics Ltd

Jun
> dom@algor.co.uk

<Prev in Thread] Current Thread [Next in Thread>