On Tue, 20 Jun 2000, Dominic Sweetman wrote:
> Yes, the original R3000 chip could be wired to produce the appearance
> of multi-word lines in its I-cache, and some derivative CPUs were built
> that way. Four was popular - I don't think anyone did 8.
DEC docs claim the cache subsystem of KN03 is configured with single-word
lines for the icache, but upon an icache fill the MB ASIC fills four
lines.
> And while I'm here, I'll continue my lonely campaign. I suggest you
> don't say "flush" because nobody knows whether it means invalidate,
> write-back, or both[1]. Instead, say "invalidate", "writeback", or
> "both". Even if it means changing St Linus' function names...
OK, by "flush" I always meant "invalidate" (see also ia32's invd and
wbinvd instructions -- the first one causes an external flush cycle and
the other one an external writeback cycle and then a flush cycle -- that's
Intel's original naming). On the other hand, "invalidate" is surely not
more ambiguous than "flush", so feel free to continue your campaign...
;-)
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
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