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Re: R5000 support (specifically two-way set-associative cache...)

To: Jun Sun <jsun@mvista.com>
Subject: Re: R5000 support (specifically two-way set-associative cache...)
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Tue, 20 Jun 2000 03:51:59 +0200
Cc: linux-mips@fnet.fr, linux@engr.sgi.com
In-reply-to: <394EA5A0.B882F66A@mvista.com>; from jsun@mvista.com on Mon, Jun 19, 2000 at 03:58:40PM -0700
References: <394EA5A0.B882F66A@mvista.com>
On Mon, Jun 19, 2000 at 03:58:40PM -0700, Jun Sun wrote:

> I looked into the R5000 support and have a couple of questions:
> 
> 1. Is R5000, specifically NEC Vr5000, fully supported?  I have seen
> CONFIG_CPU_R5000 defined, but it does not appear to do much.

Indeed, the various CPU options for the R4xxx / R5xxx CPUs mostly deal
with C compiler options as a minor optimization.

> 2. Specifically, NEC Vr5000 has two-way set-associative cache.  I
> browsed through the cache code, and got concerned that I don't see any
> code that seems to take care of that.  Do I miss something?

Yes :-)

The R5000 has R4600 style caches, so also uses the same code.

> 3. I understand Geert has a port to DDB5074 (with Vr5000 CPU).  Is this
> port completed (including all interrupts, PCI related stuff).  Is this
> port reliable?

I leave the question to Geert to answer.

  Ralf

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