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Re: Icache coherency problems for R3400, DS5000/240

To: Ralf Baechle <ralf@oss.sgi.com>
Subject: Re: Icache coherency problems for R3400, DS5000/240
From: Dominic Sweetman <dom@algor.co.uk>
Date: Tue, 20 Jun 2000 00:46:11 +0100 (BST)
Cc: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, Ralf Baechle <ralf@uni-koblenz.de>, Harald Koerfgen <Harald.Koerfgen@home.ivm.de>, linux-mips@fnet.fr, linux-mips@oss.sgi.com
In-reply-to: <20000620000455.B27454@bacchus.dhis.org>
References: <Pine.GSO.3.96.1000619110632.10348D-100000@delta.ds2.pg.gda.pl> <20000620000455.B27454@bacchus.dhis.org>
> > ... Second, it changes the assumption of the icache line size to a
> > single word -- apparently, at least R3400 of DS5000/240 has an
> > icache with such a layout (DEC docs confirm it, indeed).

Yes, the original R3000 chip could be wired to produce the appearance
of multi-word lines in its I-cache, and some derivative CPUs were built
that way.  Four was popular - I don't think anyone did 8.

> > Besides obvious bugfixes, it introduces two significant changes.
> > First, flush_icache_page() now performs what the name suggests,
> > i.e. flushes the instruction cache.

And while I'm here, I'll continue my lonely campaign.  I suggest you
don't say "flush" because nobody knows whether it means invalidate,
write-back, or both[1].  Instead, say "invalidate", "writeback", or
"both".  Even if it means changing St Linus' function names...

[1] well in this case we do, because this is an I-cache and R3000s
    only had write-through caches anyway.  But you weren't going to
    stop there, were you?

Dominic
Algorithmics Ltd
dom@algor.co.uk

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