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Re: VC exceptions

To: Joan Eslinger <wombat@kilimanjaro.engr.sgi.com>, "Kevin D. Kissell" <kevink@mips.com>, linux-mips@vger.rutgers.edu, linux-mips@fnet.fr
Subject: Re: VC exceptions
From: Bryan Manternach <smash@sgi.com>
Date: Tue, 02 May 2000 18:03:20 -0700
References: <200005022304.QAA04626@kilimanjaro.engr.sgi.com>
Sender: smash@sgi.com
Joan Eslinger wrote:
> 
>  * Date:    Tue, 2 May 2000 13:18:49 +0200
>  * From:    "Kevin D. Kissell" <kevink@mips.com>
>  *
>  * Quibble here:  The Challenge/PowerChallenge bus had
>  * little or nothing to do with VME.   I recall that it was a synchronous,
>  * "pended operation" bus, and VME is neither.
> 
> The main system bus is proprietary, called SysAD. Challenge and Power
> Challenge did support VME cards, but I don't remember if the SysAD bus
> had a VME extension on it or if you had to stick in a VME/SysAD card to
> get that.

I'm not certain if the challenge actually uses SysAD, since
it has separate address and data busses.  (big ones!) and
separate address and data bus ASICs.  SysAD is a chip
interconnect, and doesn't necessarily denote the system's
overall architechture.  Maybe if you have a R10K
Challenge...

VME on a challenge system is handled by the VCAM (VME
Channle Adapter Module) on the primary IO4.  The primary IO4
has FCI (Flat Cable Interconnect) controller chips on it that 
control interfaces to graphics(if present), Mezzanine boards,
and the VME bus.

>From the documentation:

The main set of buses in the Challenge and Onyx system architecture is the
Everest address and data buses, Ebus for short. The Ebus provides a 256-bit data
bus and a 40-bit address bus that can sustain a bandwidth of 1.2 GB per second. 

The 256-bit data bus provides the data transfer capability to support a large
number of high-performance RISC CPUs. The 40-bit address bus is also wide enough
to support 16 GB of contiguous memory in addition to an 8 GB I/O address space. 

The 64-bit Ibus (also known as the HIO bus) is the main internal bus of the I/O
subsystem and interfaces to the high-power Ebus through a group of bus
adapters.The Ibus has a bandwidth of 320 MB per second that can sufficiently
support a graphics subsystem, a VME64 bus, and as many as eight SCSI channels
operating simultaneously. 

Communication with the VME and SCSI buses, the installed set or sets of graphics
boards, and Ethernet takes place through the 64-bit Ibus. The Ibus interfaces to
the main system bus, the 256-bit Ebus, through a set of interface control
devices, an I address (IA) and four I data (ID). The ID ASICs latch the data,
and the IA ASIC clocks the data from each ID to the Flat Cable Interface (FCI)
through the F controller (or F chip).

Two FCI controllers (or F controllers) help handle the data transfers to and
from an internal graphics board set (if present) and any VMEbus boards in
optional CC3 applications. The SCSI-2 (S1) controller serves as an interface to
the various SCSI-2 buses. The Everest peripheral controller (EPC) device manages
the data movement to and from the Ethernet, a parallel port, and various types
of on-board PROMs and RAM.




-- 
"I sense much NT in you.  NT leads to Blue Screen.  Blue Screen
 leads to downtime.  Downtime leads to suffering.  NT is the path 
 to the darkside."              -- Unknown UNIX Jedi
---------------------------------------------------------------
Bryan 'SMASH' Manternach - ECS/TREX Systems Administration Team
SGI, 1200 Crittenden Pkwy, MS 30-4-175, Mountain View, CA 94943
E-mail: mailto:smash@sgi.com               Voice: (650)933-6856
 Pager: mailto:smash_p@pager.sgi.com       Pager: (650)317-8483

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