| To: | Ralf Baechle <ralf@oss.sgi.com> |
|---|---|
| Subject: | Re: Indy crashes |
| From: | "William J. Earl" <wje@cthulhu.engr.sgi.com> |
| Date: | Tue, 15 Feb 2000 09:49:19 -0800 (PST) |
| Cc: | "Kevin D. Kissell" <kevink@mips.com>, geert@linux-m68k.org, linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr, linux-mips@vger.rutgers.edu |
| In-reply-to: | <20000215011346.D828@uni-koblenz.de> |
| References: | <022301bf7730$92b87180$0ceca8c0@satanas.mips.com> <20000215011346.D828@uni-koblenz.de> |
Ralf Baechle writes:
> On Mon, Feb 14, 2000 at 10:15:02PM +0100, Kevin D. Kissell wrote:
...
> > not the way the R5000 is specified. So rather than set
> > dma_cache_wback_inv to r4k_dma_cache_wback_inv_sc
> > or r4k_dma_cache_wback_inv_pc, depending on the
> > presence or absence of a primary cache, in the MIPS
> > Technologies I bound it to a function:
>
> I don't even pretend that Linux is running on a R5000 with L2 except on
> Indy R5000SC's. These R5000 modules are different in that they don't use
> the L2 support which is part of the processor but rather use the same
> external cache implementation as the R4600SC CPU modules do.
...
If someone wants to do the real R5000SC (and RM5271 and RM7000)
cache routines, for some other platform, I can supply the required
details.
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