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Re: Indy crashes

To: "Kevin D. Kissell" <kevink@mips.com>
Subject: Re: Indy crashes
From: Ralf Baechle <ralf@oss.sgi.com>
Date: Tue, 15 Feb 2000 01:13:46 +0100
Cc: geert@linux-m68k.org, Ralf Baechle <ralf@oss.sgi.com>, linux@cthulhu.engr.sgi.com, linux-mips@fnet.fr, linux-mips@vger.rutgers.edu
In-reply-to: <022301bf7730$92b87180$0ceca8c0@satanas.mips.com>
References: <022301bf7730$92b87180$0ceca8c0@satanas.mips.com>
On Mon, Feb 14, 2000 at 10:15:02PM +0100, Kevin D. Kissell wrote:

> The problem may be in the assumption made even in the
> most recent 2.3.x code that a hit-writeback-invalidate cache
> operation on the secondary cache automagically affects the
> primary.  That's the way it is on the R4000/4400, but that's

Yep.

> not the way the R5000 is specified.  So rather than set
> dma_cache_wback_inv to r4k_dma_cache_wback_inv_sc
> or r4k_dma_cache_wback_inv_pc, depending on the
> presence or absence of a primary cache,  in the MIPS 
> Technologies I bound it to a function:

I don't even pretend that Linux is running on a R5000 with L2 except on
Indy R5000SC's.  These R5000 modules are different in that they don't use
the L2 support which is part of the processor but rather use the same
external cache implementation as the R4600SC CPU modules do.

  Ralf

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