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Virtual Indexed, Physical Tagged Cache

To: linux-mips@fnet.fr
Subject: Virtual Indexed, Physical Tagged Cache
From: Yasumasa NAKADA <yasumasa.nakada@toshiba.co.jp>
Date: Mon, 18 Oct 1999 11:35:04 +0900
Cc: nakada@cosdc.toshiba.co.jp
Hi.

Does any "Linux/MIPS" support virtual indexed physical tagged
cache?

You know, some kind of cache has the depth over 4KB (the depth of
8KB size and 2way is 4KB, the depth of 8KB size and 4way is 2KB).
For that kind of cache, "the page coloring" or some other cares
must be needed.

In the case of the page size 4KB, and cache depth 8KB, VA[12:0]
(virtual address) and PA[12:0](physical address) are different.
If some two processes use the same memory area in common, the 
area will accessed with different VA(of course same PA).
In this case the area may be refilled in the two places of the cache,
the upper area and the lower area of the cache.
If this occurs in the data cache, the data consistency may be lost.

"the page coloring" is the method for the avoidance of this condition.
The OS set the PA[12] same as VA[12]. Of Course there may be many methods
for the avoidance.

I found comments in include/asm-mips/pgtable.h:

/* Basically we have the same two-level (which is the logical three level
 * Linux page table layout folded) page tables as the i386.  Some day
 * when we have proper page coloring support we can have a 1% quicker
 * tlb refill handling mechanism, but for now it is a bit slower but
 * works even with the cache aliasing problem the R4k and above have.
 */


But I can't find the actual code for this.

Does anyone know the method for this kind of cache?

Thanks.

nakada

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