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Re: query about arch/mips/dec/irq.c (mask & unmask irq)

To: Linux MIPS mailing list <linux-mips@fnet.fr>
Subject: Re: query about arch/mips/dec/irq.c (mask & unmask irq)
From: "Paul M. Antoine" <paul@milleng.com.au>
Date: Fri, 17 Sep 1999 08:30:21 +1000
Organization: Millennium Engineering Pty Ltd
References: <Pine.LNX.3.96.990916182939.23805M-100000@skynet.csn.ul.ie> <01ea01bf0082$48bfefb0$b8119526@ltc.com>
Folks, could I make a bold suggestion?

Bradley below refered David Arlie to an email from Harald outlining how he's
managed (sneakily :-) to make the interupt code work.

Perhaps these hints as to how it works could go into the code itself to help
other hapless hackers?????

I know it's a lot to ask for documentation in the code, but hey, I'm just
software quality assurance mad really!!! :-)

Paul


"Bradley D. LaRonde" wrote:
> 
> Hehe, I asked the same question a while back, at which time Harald
> prounounced this blessing upon it:
> 
> ---------
> 
> It's nonexistant by purpose.
> 
> I tried to write an irq handler which is abstract enough to work on five
> completely different machines wrt IRQs (thus the somewhat nontransparent
> setup routines in arch/mips/dec/setup.c). Some DECstations have an IOASIC
> which is wired to one of the six CPU hardware interrupts. The IOASIC handles
> up to 32 interrupts itself.
> 
> arch/mips/kernel/head.S disables the CPU interrupts, so when the first
> IOASIC interrupt is unmasked, the appropriate CPU interrupt is
> unconditionally enabled as well and will never be disabled again because
> another IOASIC interrupt may be enabled.
> 
> I am simply relying on the assumption that the IOASIC will not generate an
> interrupt if all interrupts are disabled in the IOASIC itself and it seems
> to work.
> 
> ----------
> 
> :-)
> 
> Regards,
> Brad
> 
> ----- Original Message -----
> From: Dave Airlie <airlied@csn.ul.ie>
> To: <linux-mips@fnet.fr>
> Sent: Thursday, September 16, 1999 12:31 PM
> Subject: query about arch/mips/dec/irq.c (mask & unmask irq)
> 
> >
> > In the DECstation irq.c code
> >
> > mask_irq does
> >     if (dec_interrupt[irq_nr].iemask) {         /* This is an ASIC
> > interrupt    */
> >         *imr &= ~dec_interrupt[irq_nr].iemask;
> >         dummy = *imr;
> >         dummy = *imr;
> >     } else                      /* This is a cpu interrupt        */
> >         set_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) &
> > ~dec_interrupt[irq_nr].cpu_mask);
> >
> > and unmask does
> > if (dec_interrupt[irq_nr].iemask) {         /* This is an ASIC interrupt
> > */
> >         *imr |= dec_interrupt[irq_nr].iemask;
> >         dummy = *imr;
> >         dummy = *imr;
> >     }
> >     set_cp0_status(ST0_IM, read_32bit_cp0_register(CP0_STATUS) |
> > dec_interrupt[irq_nr].cpu_mask);
> >
> > Note the else in the mask_irq code but not in the unmask, does this matter
> > at all ? or should the else on the other one be there ?
> >
> > Dave.
> >
> > ------------ David Airlie, David.Airlie@ul.ie,airlied@skynet --------
> > Telecommunications Research Centre, ECE Dept, University of Limerick \
> > http://www.csn.ul.ie/~airlied -- Telecommunications Researcher      \
> > --- TEL: +353-61-202695 -----------------------------------------------
> >

-- 
Paul
______________________________________________________________________________
Paul M. Antoine                                 Millennium Engineering Pty Ltd
email: paul@milleng.com.au                              Phone: +61 2 9560 7331
large files: pantoine@nsw.bigpond.net.au                Fax:   +61 2 9560 8708

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