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Re: Memory corruption

To: "William J. Earl" <wje@fir.engr.sgi.com>
Subject: Re: Memory corruption
From: "Gleb O. Raiko" <raiko@niisi.msk.ru>
Date: Thu, 08 Jul 1999 13:27:03 +0400
Cc: Warner Losh <imp@village.org>, Harald Koerfgen <Harald.Koerfgen@home.ivm.de>, Ralf Baechle <ralf@uni-koblenz.de>, linux-mips@vger.rutgers.edu, linux-mips@fnet.fr, linux@cthulhu.engr.sgi.com, Ulf Carlsson <ulfc@thepuffingroup.com>
Organization: NIISI RAN
References: <XFMail.990707230857.Harald.Koerfgen@home.ivm.de> <199907080151.TAA05482@harmony.village.org> <14212.5891.237364.112104@fir.engr.sgi.com>
"William J. Earl" wrote:
> 
> Warner Losh writes:
>  > In message <XFMail.990707230857.Harald.Koerfgen@home.ivm.de> Harald 
> Koerfgen writes:
>  > : That's definitely true for R3k DECstations, and no, flushing the icache 
> in
>  > : flush_tlb_page() does not help. I have added cacheflushing to all tlb 
> routines,
>  > : copy_page and even rw_swap_page_base() and swap_after_unlock_page() 
> without
>  > : success.
>  >
>  > Don'y you want to flush the dcache as well?  I think that you can run
>  > into problems when you have a dirty dcache and then dma into the pages
>  > that are dirty.  Instant karma corruption, no?  Or am I thinking of
>  > some other problem?
> 
>       The R3000 has a write-through cache, so there cannot be dirty cache
> lines, although you do have to flush the write buffers to be completely
> correct (in the case of a DMA device writing to memory VERY quickly after
> the register write which starts it up, on some hardware).

You must flush d-cache after dma. While some cache controllers are able
to watch the bus and flush the data that are invalidated due to DMA
transfers, I think, most r3k boxes doesn't have such beasts. Flushing
d-cache wasn't implemented at the same time as the cache stuff because
we hadn't boxes with DMA devices.

Regards,
Gleb.

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