"William J. Earl" wrote:
> Warner Losh writes:
> > In message <XFMail.990707230857.Harald.Koerfgen@home.ivm.de> Harald
> Koerfgen writes:
> > : That's definitely true for R3k DECstations, and no, flushing the icache
> > : flush_tlb_page() does not help. I have added cacheflushing to all tlb
> > : copy_page and even rw_swap_page_base() and swap_after_unlock_page()
> > : success.
> > Don'y you want to flush the dcache as well? I think that you can run
> > into problems when you have a dirty dcache and then dma into the pages
> > that are dirty. Instant karma corruption, no? Or am I thinking of
> > some other problem?
> The R3000 has a write-through cache, so there cannot be dirty cache
> lines, although you do have to flush the write buffers to be completely
> correct (in the case of a DMA device writing to memory VERY quickly after
> the register write which starts it up, on some hardware).
You must flush d-cache after dma. While some cache controllers are able
to watch the bus and flush the data that are invalidated due to DMA
transfers, I think, most r3k boxes doesn't have such beasts. Flushing
d-cache wasn't implemented at the same time as the cache stuff because
we hadn't boxes with DMA devices.