On Fri, Oct 16, 1998 at 12:44:42PM +0200, Harald Koerfgen wrote:
> Your problem might be another one. The R3000 Family processors (including the
> R2000)
> have a four word writeback buffer which usually is transparent to memory
> accesses,
> but may have side effects when dealing with hardware registers.
>
> Example: Let's assume data and status to be two hardware registers and writing
> something to data has an influence on the content of the status register. A
> code
> snippet like:
>
> data = whatever;
> if (status == OK)
> do_something();
>
> might fail because it cannot be guaranteed that the write access to data
> happens
> before the read access from status.
>
> The solution to this problem is to wait until the writeback buffer is empty
> i.e.,
> all write accesses are done. Unfortunately the mechanism for this is hardware
> implementation specific and the DECstation engineers chose four different
> ways to do
> this. You might want to look at arch/mips/dec/wbflush.c.
>
> To make a long story short, the above code snippet should look like:
>
> #include <asm/dec/wbflush.h>
>
> data = whatever;
> wbflush();
> if (status == OK)
> do_something();
>
>
> If you have to write to several hardware registers in a certain sequence, you
> have
> to wait for the writeback buffer to be empty too. For example:
>
> reg_1 = a_value;
> wbflush();
> reg_2 = another_value;
>
> when the access to reg_1 should be done before the access to reg_2.
Harald, will this problem make any changes to code used also for the
R4000 necessary?
Ralf
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