> Most caches today on other architectures are virtual indexed;
> they're usually just implemented somewhat more clever such that they
> feel like physical indexed caches to the OS.
It's common practice to restrict the cache set size to match the
memory translation page size, so that only in-page addresses are used
in the cache index - so from the index point of view virtual and
physical addresses are the same. Is that what you meant? I can't see
any other way of avoiding aliases in a virtually-indexed
The RM7000 has no aliases because it's 16Kbyte caches are 4-way set
associative - 4Kbyte sets, equal to the page size. However, that's
only possible with the RM7000's relatively small primary cache, which
in turn is practicable because it also has an onchip secondary cache.
I recall the first SuperSPARC chip had a 5-way set-associative 20Kbyte
cache for the same reason.