> I don't have a machine with a SC CPU, so I hopbe somebody of you can
> help me -- the manuals of the R4000 / R4400 documents that the L2 cache
> is tagged with bits 12-14 of the virtual address. This is somewhat
> strange because only cache-size / 4kb bits are required to avoid virtual
> aliases. That would be 1 bit for the R4000SC and 2 bits for the R4400SC.
> Question: will the R4000SC/R4400SC actually verify 3 bits or only the
> one rsp. two bits which need to be checked?
Yes, they verify all 3 bits. You can have a VCE handler, even for
kernel stacks, if you are very careful in the general exception handler.
(The VCE handler does writeback invalidate on the primary data cache and
an invalidate on the primary instruction cache for the offending address,
and then does a hit-set-virtual on the secondary cache; alternately, somewhat
more slowly, but more simply, the handler does a writeback invalidate on the
secondary cache.) Of course, you still have to arrange to have only
one virtual color valid at a time for a given physical page to make
the R4000PC, R4600, and R5000 work correctly. On the other hand, if you
can arrange that, including flushing the cache appropriately when changing
the current virtual color of a physical page, you will never get a VCE
(assuming you treat the R4000SC and R4400SC has having 8 colors, not 2 or
On the other processors, where VCE is not detected, you can
further optimize the code by allowing for multiple virtual colors for
read-only pages, invalidating all conflicting mappings when a
read-write mapping is required. IRIX does this in 6.3 and 6.5. We
don't break the mappings; we just turn off pg_vr in the PTEs. When we
get a fault on one of the software-valid, hardware-invalid mappings,
we do an ownership switch, turning off the mappings for the current
color and changing the current color to the desired one. This of
course requires appropriate cache cleaning for the whole page.
By comparison, the R4000SC/R4400SC VCE handler works just one cache
line at a time.