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Re: Lmbench results for Linux/MIPS 2.1.90

To: ralf@uni-koblenz.de
Subject: Re: Lmbench results for Linux/MIPS 2.1.90
From: "William J. Earl" <wje@fir.engr.sgi.com>
Date: Sun, 22 Mar 1998 21:30:05 -0800
Cc: linux-mips@fnet.fr, linux-mips@vger.rutgers.edu, linux@cthulhu.engr.sgi.com, lm@who.net
In-reply-to: <19980322075452.09681@uni-koblenz.de>
References: <19980322075452.09681@uni-koblenz.de>
ralf@uni-koblenz.de writes:
 > Hi all,
 > 
 > here is another round of lmbench results.  Most notably all benchmarks
 > that depend on the overhead of syscall entry have improved remarkably.
 > For comparison I've included some more machines in the table.
 > 
 > The machines:
 > 
 >  indy:     Indy R5000SC 180MHz, 512mb l2 cache, 96mb memory.
 >  sv002076: Sun Ultra Enterprise E450, 2 x 296MHz Ultra2 CPUs,
 >            1gb memory (two interleaved).
 >  dull:     Dell Pentium 200 MMX, 32mb, running Redhat's 2.0.27.
 >  tbird:    SNI RM200, R4600 133MHz, no second level cache, 32mb memory.
 > 
 > I'm thinking about not saving the temporary registers on syscall entry;
 > I'm just not shure if this would break the semantics of ptrace(2).
...

      UMIPS-BSD (4.3 BSD on the MIPS M/1000) did not save the temporary
registers on syscall().  It did, of course, save them on interrupts,
so preemption left the registers valid.  I don't see why saving the
registers on syscall should affect ptrace(), since the ptrace()
caller is acting on another process, which will have saved all its
registers if preempted.  That change ought to let the R5000 beat
the Pentium, despite the Indy's miserable memory latency.

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