> Hi all,
> I think I found the bug causing the reported R4000SC/R4400SC crashes.
> In r4kcache.h some of the functions for handling the second level caches
> were using the wrong cacheops.
> I'm rewriting the thing; the file was producing a huge object file and
> not able to handle primary instruction and data caches with different
> linesize. This was a problem with the Vr4300 and some Magnum 4000 and
> the Olivetti M700 where reconfiguring the linesize of the primary cache
> isn't advisable.
> What I won't fix for now is the handling of split instruction and data
> second level caches a la R4000SC. I don't know of any system using
> something like this.
I don't know about other vendors, but all MIPS and SGI systems had
unified secondary caches. It is indeed the case that reconfiguruing
the linesize on the MIPS Magnum systems is not advisable, at least on
the older revisions of the memory controller. (Various combinations mostly
worked, but only some worked all the time.) As far as I know, all systems
shipped were correctly configured.