Perhaps I should have added: when rewriting R3K exception handlers,
you need to be aware that the way you get into the general exception
entry point is very different.
When the R4K CPUs get a TLB miss during the fast TLB miss exception
routine, they leave the original user exception restart location in
EPC. When you get to the general exception handler, it's as if
the fast TLB exception never happened.
The R3K doesn't do that; it nests the second-level miss exception and
returns back through the fast handler. The MIPS OS' handlers use one
of the reserved-for-exception registers (k0, k1) to save the original
That's why MIPS reserved two registers for exceptions...