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Re: working 2.1.36 on magnum/m700 ?

To: linux-mips@fnet.fr
Subject: Re: working 2.1.36 on magnum/m700 ?
From: "David S. Miller" <davem@jenolan.rutgers.edu>
Date: Tue, 3 Jun 1997 05:00:51 -0400
In-reply-to: <199706030752.IAA00252@gladsmuir.algor.co.uk> (message from Dom Sweetman on Tue, 3 Jun 1997 08:52:00 +0100 (BST))
   Date: Tue, 3 Jun 1997 08:52:00 +0100 (BST)
   From: Dom Sweetman <dom@algor.co.uk>

   If your system is bizarre enough to put hardware registers outside
   this easily-accessible physical address range, you would indeed
   need either special TLB entries (or real 64-bit pointers on an
   R4x00).  In this case not even Ralf would disagree with wiring
   those entries; but a better solution would be to fire the hardware
   designer and incinerate the hardware.

I don't see what the big deal is.  Just use tlb entries for the memory
mapped I/O registers, and let them tlb miss in.  I remember my tlb
miss code is around 12 instructions or so.

I use dynamic tlb replacable entries for memory mapped I/O on the
UltraSparc and those misses can cost around 20 instructions or so for
a kernel miss.

It pays off to do this really, when I/O registers aren't being
accessed, the tlb entires become available for the user, if they are
being often accessed the tend to sit "hot" in the tlb and don't get
kicked out much.  There is no gain to be had by locked them down.

---------------------------------------------////
Yow! 11.26 MB/s remote host TCP bandwidth & ////
199 usec remote TCP latency over 100Mb/s   ////
ethernet.  Beat that!                     ////
-----------------------------------------////__________  o
David S. Miller, davem@caip.rutgers.edu /_____________/ / // /_/ ><

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