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Re: Delay Slot

To: linux-mips
Subject: Re: Delay Slot
From: Miguel de Icaza <miguel@nuclecu.unam.mx>
Date: Mon, 14 Apr 1997 23:02:14 -0500
In-reply-to: <199704150343.XAA00982@jenolan.caipgeneral> (davem@jenolan.rutgers.edu)
> Ok, that was the second case, here comes where they fucked things up
> massively on the MIPS.  Aparently they thought it was a "nice" idea to
> hide the delay instruction mechanism of the cpu to the user by default
> in most MIPS assemblers.  Therefore, by default when you feed
> instructions to most MIPS assemblers the delay slots do not exist, the
> assembler schedules the instructions and fills the delay slots for
> you, so in this case you'd code as if it were a non-delay slotted
> architecture.

Well, it makes the programmer's life easier.  

There is a very nice book that talks about some of the MIPS design
issues (computer architecture something by Patterson and Hennesey).  I
liked the idea that the programmer is freed from having to keep in
mind the MIPS tricks for the boring parts of the code. 

Seasoned programmers put a .set noreorder at the top of their assembly
files and gcc __asm__ macros.

> And further still, some assemblers have 'noreorder' set by default,
> most do not.  You'll need to consult the docs for the assembler you
> are using to see which is the case.

Hopefully, the MIPS assemblers have a nice warning system.  

The Alpha has exactly the same problem.

> I was pretty ticked when I learned that MIPS assemblers move
> instructions around on you behind your back, this is just simply
> broken.

You mean the usage of the at register for performing the syntetic
instructions?  Yeah, well, I can imagine *you* did not like that :-).
But you never liked syntetic instructions on the sparc either.

Miguel.



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