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Re: Almost got 2.1.14.2 to a patchable stage...

To: linux-mips
Subject: Re: Almost got 2.1.14.2 to a patchable stage...
From: Miguel de Icaza <miguel@nuclecu.unam.mx>
Date: Fri, 11 Apr 1997 15:12:55 -0500
In-reply-to: <236.199704111034@gladsmuir.algor.co.uk> (message from Dom Sweetman on Fri, 11 Apr 1997 11:34:27 +0100 (BST))
> It's worse than that; MIPS[1234] only prescribes the user-level
> behaviour of the CPU.  The bits of the CPU which only the kernel deals
> with (what MIPS calls "co-processor 0") are implementation dependent.

That is not very different from other RISC chips.  This sounds a lot
like the SPARC mmus :-).

> o All Linux-capable MIPS-3 CPUs are readily driven with the same
>   software.  Some detailed differences (R4400 likes more nops than
>   R4600 sometimes), but nothing serious.
> 
> You will need ifdefs for MIPS-1 vs MIPS-3 in any code which messes
> with the interrupt levels or TLB.

Nope.  The code is ready to load implementation specific mmu routines
at any time.  You just use function pointers to call the
implementation specific routines.

> And there again it's worse, because you'll search in vain for any
> systematic documentation about this.

¿Mhm?  To me it looked like quite well documented last time I went ftp
hunting for information.  {ftp,www}.{sgi,mips}.com on of those keeps
any ammount of information on the processor specific stuff.  They even
document bugs in some specific editions of the MIPS chips (unlike the
SPARC chips, where DaveM had to go bug hunting for them).

Cheers,
Miguel.

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