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Re: Almost got 2.1.14.2 to a patchable stage...

To: linux-mips
Subject: Re: Almost got 2.1.14.2 to a patchable stage...
From: Dom Sweetman <dom@algor.co.uk>
Date: Fri, 11 Apr 1997 18:59:27 +0100 (BST)
In-reply-to: <199704111158.NAA00930@kernel.panic.julia.de>
References: <236.199704111034@gladsmuir.algor.co.uk> <199704111158.NAA00930@kernel.panic.julia.de>
Ralf,

It's time for MIPS theology!

> Wrong :-)  IDT offers a R3000 derived CPU plus the MIPS II extensions ...

Outside floating point, there's only a few differences from MIPS-1 to
MIPS-2:

o "Branch-likely" forms of branches, for more efficient loop closing.
  
o 'cache' operations - which could possibly be regarded as
  CPU-specific, anyway.

o load-linked/store-conditional (MIPS'semaphore instructions).

LSI included these in their miniRISC, which they described as "32-bit
R4000" CPUs.  LSI put them in in the belief they'd get better code
density, which you don't; branch-likely permits you to replace a nop
with a duplicated instruction, saving a clock but no space.  Toshiba's
R3900 also picked up branch-likely, which is likely to become common
on future 32-bit MIPS CPUs.

I'd have said this makes miniRISC and R3900 about MIPS one-and-a-third.

No 32-bit CPU implements 'cache' or semaphores.  IDT's 32-bit machines
are all MIPS-1.

> And I think the MIPS II extensions are interesting.

You're entitled to your opinion there... I though they were kind of
cute myself, particularly the semaphores.

Dominic Sweetman
dom@algor.co.uk

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