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Re: Almost got 2.1.14.2 to a patchable stage...

To: linux-mips
Subject: Re: Almost got 2.1.14.2 to a patchable stage...
From: Warner Losh <imp@village.org>
Date: Fri, 11 Apr 1997 10:30:49 -0600
In-reply-to: Your message of "Fri, 11 Apr 1997 15:12:55 CDT." <199704112012.PAA15643@athena.nuclecu.unam.mx>
References: <199704112012.PAA15643@athena.nuclecu.unam.mx>
In message <199704112012.PAA15643@athena.nuclecu.unam.mx> Miguel de
Icaza writes: 
: Nope.  The code is ready to load implementation specific mmu routines
: at any time.  You just use function pointers to call the
: implementation specific routines.

Yuck.  On a TLB miss?  You must be joking :-).  Actually, since the
TLB miss stuff is at a hard wired address, a simple bcopy of PIC code
would do the right thing on boot.  NetBSD was moving in this direction
when I last checked out their source base 6-9 months ago.

: > And there again it's worse, because you'll search in vain for any
: > systematic documentation about this.
: 
: ¿Mhm?  To me it looked like quite well documented last time I went ftp
: hunting for information.  {ftp,www}.{sgi,mips}.com on of those keeps
: any ammount of information on the processor specific stuff.  They even
: document bugs in some specific editions of the MIPS chips (unlike the
: SPARC chips, where DaveM had to go bug hunting for them).

Well the problem isn't that the information isn't there.  The problem
is that no one has written up a good tretis on what the differences
are.  We get things like "The Sky is Blue on the R4000" and then in
andother document, burried we see that it is really turquoise on the
R5000.  Unless we had read carefully and remembered the R4000
document, you'd not know what the differences are.  This gets worse
when you start bringing in all the oddball 4x chips (some of which
don't even have an MMU) and the R5x and R10x chips.

Once you go through it five or ten times, it ibecomes second nature,
but it is a hard learning curve to climb.

Warner

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