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Re: r10000 boards

To: linux-mips
Subject: Re: r10000 boards
From: Systemkennung Linux <linux@informatik.uni-koblenz.de>
Date: Wed, 2 Apr 1997 14:49:34 +0200 (MET DST)
In-reply-to: <Pine.LNX.3.95.960401194650.11590A-100000@ravage.labs.gmu.edu> from "Ryan Rafferty" at Apr 1, 96 07:49:54 pm
Hi,

> > A good RAM interface is a much more effective mean to accelerate a system 
> > than
> > caches especially when you have an application that has a working set that
> > exceeds the cache size.  The Magnum's RAM interface may be slow by today's
> > standards but it was very fast at it's time.
> 
> Ok, that's cool.  But then why do computer manufacturers still incorporate
> cache into today's machines instead of using blazing memory interfaces?

For i486 machines there was a chipset which in most real world benchmarks was
outrunning all other machines with or without L2 cache just because of
a RAM interface with all tricks in the book.  Damn, can't remember it's
name ...

> For example, the fastest Alpha computers today have 8 megs of static RAM
> cache.  If a faster memory interface would have eliminated the need for
> it, why didn't they use it?

Caches aren't completly useless.  Cache are cheaper than an expensive
motherboard (many connections for interleaving memory banks), many
fast SIMMs etc.  If you want to build a 0 wait state memory system for
a 25MHz 68030 (off topic ... but that's the last DRAM bank I really
poked my nose in ...) you need 25ns DRAM (whoops, they don't exist ...)

Another point for caches is that they're made of static RAMs.  Static
RAMs are relativly easy to handle, don't need refresh etc.  DRAMs
have three access times: the one on the data sheet, a RAS access
time (which is shorter than the first one) and a CAS access time which
is longer than the data sheet axs time).  If you access a DRAM with
a random pattern you will have to deal mostly with the CAS time which
is _slow_.  The cache SRAM deal with that better than DRAMs - but
only if you have cache hits ...

Next effect of caches is that they keep the memory bus activity lower.
This is important for systems with multiple bus masters because it
will reduce the latency until a memory bus transaction is completed.

Afaik Crays (the real ones, not those MPP kludges ;-) don't have
caches.  When you have a working set in the gigabyte range caches are
just a waste of silicon that slows your bus down ...

  Ralf

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