linux-mips-fnet
[Top] [All Lists]

Re: Cascade interrupt

To: linux-mips@fnet.fr
Subject: Re: Cascade interrupt
From: Warner Losh <imp@village.org>
Date: Tue, 21 May 1996 09:06:51 -0600
In-reply-to: Your message of Tue, 21 May 1996 14:15:15 +0200
: I'd assume the firmware initializes them correctly.  Big trick with this
: cascade mode is that the interrupt output of PIC 2 is wired to interrupt
: input 2 of PIC 1 and then some cascade bit is set via software.  I've
: lost my data sheets when I left at Waldorf, so everything is just from
: memory ...

OK.  I understand what you are saying now.  When the IRQ 2 interrupt
happens, it means that I have to manually go out and check interrupts
8-15 rather than having it just happen.

:                 beq     a0,2,poll_second                # cascade?
:                 li      s1,1                            # delay slot
:     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^  Insert these two lines

Hmmm, similar lines in rpc44.S do indeed solve the problem.  My
Buslogic card seems to be properly initialized.  Or at least the
interrupts for it are happening now.  It is having some problems on a
bare naked scsi bus (well, one that has one device off attached
externally), but I'm checking now with a populated scsi bus.

Hmmm.  I have a target 3 drive on the bus, properly terminated, and am
seeing that it is aboriting commands and resetting the bus.  I get a
lot of bus reset for host 0 messages.  In fact, all the commands seem
to be coming back with all 0's.  Hmmm, well, at least it is progress
:-).

Warner

<Prev in Thread] Current Thread [Next in Thread>