linux-mips-fnet
[Top] [All Lists]

Cascade interrupt

To: linux-mips@fnet.fr
Subject: Cascade interrupt
From: Systemkennung Linux <linux@mailhost.uni-koblenz.de>
Date: Tue, 21 May 1996 04:26:48 +0200 (MET DST)
Hi all,

while playing around with the RM200 I had to find out that some of the
"RISC PC" class machines use the PICs in cascade mode while others don't.
This is completly opposed the the standard Intel PC design where the PICs
are always in cascade mode.  So just in case if you wonder why your
machine never gets high interrupts (>= 8) check this.

   Ralf

<Prev in Thread] Current Thread [Next in Thread>