> Bizarre. It should take 2 cycles/loop on *any* R4600, and 4
> cycles/loop on an R4000/4400. I'd put money on it *not* taking one
> cycle/loop - only an R10000 can do that! There are some unlikely
> reasons I can think of for the difference (eg the loop spans a page
> boundary and is in mapped space, when it will repeatedly have to do a
> micro-tlb refill - but I'm sure you're in unmapped space).
Yes, you're right; this effect is bizzare and cannot be explained with some
pagefill effect because it is running in KSEG0. If this machine wouldn't be
that PC-like I'd say the timers are running at a different clock. So I'll
check this timer...
> > There are two versions of the R4600; my Tyne had version 1.0 as far as
> > I remember while the SNI box has version 2.0. The 2.0 chip has some
> > bugfixes; most important is probably the way it accesses primary caches.
> > This bug can be worked around by disabeling interrupts during cacheflush
> > or (untested ...) flushing way B before way A of the cache.
> I don't recall anything on the published Rev 1 buglist which would
> affect this. Now you've got me intrigued... I'd better go look this up!
I wouldn't wonder if thisone isn't documented. Write me if you don't find it
in the docs.