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CVS Update@-mips.org: linux

To: linux-cvs@linux-mips.org
Subject: CVS Update@-mips.org: linux
From: ralf@linux-mips.org
Date: Thu, 6 Nov 2003 04:48:13 +0000
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 03/11/06 04:48:13

Modified files:
        arch/mips/sni  : irq.c 

Log message:
        The RM200's custom chip is called ASIC PCI, so renamed it in
        pciasic_irq_type.  Disable CPU IRQ1 while processing a SCSI interrupt.
        As a side effect this will also disable EISA interrupts, including the
        timer interrupt but that's the best we can do, blame the hardware
        designers.  Mask out PCI interrupts in IRQ3 handler, anything else
        should be dealt with in the respectiv handlers.


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