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CVS Update@-mips.org: linux

To: linux-cvs@linux-mips.org
Subject: CVS Update@-mips.org: linux
From: ralf@linux-mips.org
Date: Sat, 26 Apr 2003 04:18:21 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 03/04/26 04:18:21

Modified files:
        arch/mips/kernel: entry.S 
        arch/mips/mm   : c-r4k.c tlbex-r4k.S 
        arch/mips64/kernel: r4k_genex.S 
        arch/mips64/mm : c-r4k.c tlb-glue-sb1.S tlbex-r4k.S 
        drivers/char   : sb1250_duart.c 
        include/asm-mips: war.h 
        include/asm-mips64: war.h 

Log message:
        Redo R4600 workaround based on new information from PMC-Sierra.  This
        improves interrupt latency significantly and fixes another problem with
        the old workaround so should be considered a critical upgrade for R4600
        systems.
        
        Apply CPU workarounds only to those machines which were actually shipped
        with the affected processors.  As for the R4600 the assumption is only
        IP22 was shipped with V1.7 and V2.0 processors and SNI RM200C only with
        V2.0 processors; for all other systems the workarounds are disabled.
        
        Control workarounds based on value of the preprocessor symbol, not
        based on it's definedness.
        
        Move R5432 workaround to the (hopefully ...) right place and copy it
        to those places where it was missing.


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