CVS Update@-mips.org: linux

[ralf@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 03/04/15 15:19:22

Modified files:
        arch/mips/kernel: cpu-probe.c proc.c traps.c 
        arch/mips64/kernel: cpu-probe.c proc.c traps.c 
        include/asm-mips: cpu.h processor.h 
        include/asm-mips64: cpu.h processor.h 

Log message:
        Shuffle the ll/sc emulation around until it looks like having a chance
        of working.  The code used to be in the RI handler but ll and sc having
        the opcodes of lwc0 and swc0 will not cause reserved instruction but
        coprocessor unusable exceptions on processors that don't support these
        instructions.