| To: | linux-cvs@linux-mips.org |
|---|---|
| Subject: | CVS Update@-mips.org: linux |
| From: | ralf@linux-mips.org |
| Date: | Mon, 14 Apr 2003 01:33:11 +0100 |
| Reply-to: | linux-mips@linux-mips.org |
| Sender: | linux-cvs-bounce@linux-mips.org |
CVSROOT: /home/cvs
Module name: linux
Changes by: ralf@ftp.linux-mips.org 03/04/14 01:33:11
Modified files:
include/asm-mips: Tag: linux_2_4 processor.h
include/asm-mips64: Tag: linux_2_4 processor.h
arch/mips/mm : Tag: linux_2_4 c-r4k.c
arch/mips64/mm : Tag: linux_2_4 c-r4k.c
Log message:
Teach cache code about processors that can do I-cache refills directly
from the D-cache. And now back to the original project that started
all the cache cleanups - the signal code ...
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