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Coprocessors other than 1

To: "Ralf Baechle" <ralf@oss.sgi.com>, <linux-cvs@oss.sgi.com>
Subject: Coprocessors other than 1
From: "Kevin D. Kissell" <kevink@mips.com>
Date: Sat, 8 Sep 2001 17:44:22 +0200
References: <200109072335.f87NZwO22391@oss.sgi.com>
Sender: owner-linux-cvs@oss.sgi.com
> Modified files:
> arch/mips64/kernel: traps.c 
> arch/mips/kernel: traps.c 
> 
> Log message:
> Skip over copX instructions for X != 1 also.

I'm sure there's a story behind this of which I am not aware,
but surely skippling COP2 or COP3 instructions can't be
correct behavior.  Either there is no such coprocessor, in
which case SIGILL would seem to me to be appropriate,
or there really is some application-specific coprocessor
on the COP2 interface.  If such a coprocessor exists, and
has context that the kernel doesn't know how to save and
restore, until such time as we develop kernel modules to
handle them, wouldn't it be more practical to allow exactly
one processor to "own" the coprocessor?  In that model,
the first thread to issue a COP2 instruction would get it
enabled and restart the instruction, but until that thread
terminates, all other requestors would get nailed with
SIGILL or some more appopriate signal.

            Regards,

            Kevin K.


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