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CVS Update@linux-mips.org: linux

To: linux-cvs-patches@linux-mips.org
Subject: CVS Update@linux-mips.org: linux
From: ppopov@linux-mips.org
Date: Fri, 23 Sep 2005 02:47:48 +0100
Reply-to: linux-mips@linux-mips.org
Sender: linux-cvs-patches-bounce@linux-mips.org
CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ppopov@ftp.linux-mips.org       05/09/23 02:47:41

Modified files:
        drivers/mtd/nand: Kconfig au1550nd.c 
        include/asm-mips/mach-db1x00: db1200.h db1x00.h 
        include/asm-mips/mach-pb1x00: pb1200.h pb1550.h 

Log message:
        - cleaned up the include files and partitions
        - added more flexible CS setup and detection
        
        Tested on db1200 and db1550. Pushed the nand driver upstread in
        mtd head.

diff -urN linux/drivers/mtd/nand/Kconfig linux/drivers/mtd/nand/Kconfig
--- linux/drivers/mtd/nand/Kconfig      2005/07/13 11:49:46     1.8
+++ linux/drivers/mtd/nand/Kconfig      2005/09/23 01:47:41     1.9
@@ -59,8 +59,8 @@
        tristate
 
 config MTD_NAND_AU1550
-       tristate "Au1550 NAND support"
-       depends on SOC_AU1550 && MTD_NAND
+       tristate "Au1550/1200 NAND support"
+       depends on (SOC_AU1200 || SOC_AU1550) && MTD_NAND
        help
          This enables the driver for the NAND flash controller on the
          AMD/Alchemy 1550 SOC.
diff -urN linux/drivers/mtd/nand/au1550nd.c linux/drivers/mtd/nand/au1550nd.c
--- linux/drivers/mtd/nand/au1550nd.c   2005/04/14 11:31:26     1.4
+++ linux/drivers/mtd/nand/au1550nd.c   2005/09/23 01:47:41     1.5
@@ -22,13 +22,7 @@
 
 /* fixme: this is ugly */
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 0)
-#include <asm/mach-au1x00/au1000.h>
-#ifdef CONFIG_MIPS_PB1550
-#include <asm/mach-pb1x00/pb1550.h> 
-#endif
-#ifdef CONFIG_MIPS_DB1550
-#include <asm/mach-db1x00/db1x00.h> 
-#endif
+#include <asm/mach-au1x00/au1xxx.h>
 #else
 #include <asm/au1000.h>
 #ifdef CONFIG_MIPS_PB1550
@@ -46,39 +40,22 @@
 static void __iomem *p_nand;
 static int nand_width = 1; /* default x8*/
 
-#define NAND_CS 1
-
 /*
  * Define partitions for flash device
  */
 const static struct mtd_partition partition_info[] = {
-#ifdef CONFIG_MIPS_PB1550
-#define NUM_PARTITIONS            2
-       { 
-               .name = "Pb1550 NAND FS 0",
-               .offset = 0,
-               .size = 8*1024*1024 
-       },
-       { 
-               .name = "Pb1550 NAND FS 1",
-               .offset =  MTDPART_OFS_APPEND,
-               .size =    MTDPART_SIZ_FULL
-       }
-#endif
-#ifdef CONFIG_MIPS_DB1550
-#define NUM_PARTITIONS            2
        { 
-               .name = "Db1550 NAND FS 0",
+               .name   = "NAND FS 0",
                .offset = 0,
-               .size = 8*1024*1024 
+               .size   = 8*1024*1024 
        },
        { 
-               .name = "Db1550 NAND FS 1",
+               .name   = "NAND FS 1",
                .offset =  MTDPART_OFS_APPEND,
-               .size =    MTDPART_SIZ_FULL
+               .size   =    MTDPART_SIZ_FULL
        }
-#endif
 };
+#define NB_OF(x)  (sizeof(x)/sizeof(x[0]))
 
 
 /**
@@ -340,11 +317,13 @@
 /*
  * Main initialization routine
  */
-int __init au1550_init (void)
+int __init au1xxx_nand_init (void)
 {
        struct nand_chip *this;
        u16 boot_swapboot = 0; /* default value */
        int retval;
+       u32 mem_staddr;
+       u32 nand_phys;
 
        /* Allocate memory for MTD device structure and private data */
        au1550_mtd = kmalloc (sizeof(struct mtd_info) + 
@@ -365,8 +344,11 @@
        au1550_mtd->priv = this;
 
 
-       /* MEM_STNDCTL: disable ints, disable nand boot */
-       au_writel(0, MEM_STNDCTL);
+       /* disable interrupts */
+       au_writel(au_readl(MEM_STNDCTL) & ~(1<<8), MEM_STNDCTL);
+ 
+       /* disable NAND boot */
+       au_writel(au_readl(MEM_STNDCTL) & ~(1<<0), MEM_STNDCTL);
 
 #ifdef CONFIG_MIPS_PB1550
        /* set gpio206 high */
@@ -398,19 +380,60 @@
        }
 #endif
 
-       /* Configure RCE1 - should be done by YAMON */
-       au_writel(0x5 | (nand_width << 22), 0xB4001010); /* MEM_STCFG1 */
-       au_writel(NAND_TIMING, 0xB4001014); /* MEM_STTIME1 */
-       au_sync();
-
-       /* setup and enable chip select, MEM_STADDR1 */
-       /* we really need to decode offsets only up till 0x20 */
-       au_writel((1<<28) | (NAND_PHYS_ADDR>>4) | 
-                       (((NAND_PHYS_ADDR + 0x1000)-1) & (0x3fff<<18)>>18), 
-                       MEM_STADDR1);
-       au_sync();
+       /* Configure chip-select; normally done by boot code, e.g. YAMON */
+#ifdef NAND_STCFG
+       if (NAND_CS == 0) {
+               au_writel(NAND_STCFG,  MEM_STCFG0);
+               au_writel(NAND_STTIME, MEM_STTIME0);
+               au_writel(NAND_STADDR, MEM_STADDR0);
+       }
+       if (NAND_CS == 1) {
+               au_writel(NAND_STCFG,  MEM_STCFG1);
+               au_writel(NAND_STTIME, MEM_STTIME1);
+               au_writel(NAND_STADDR, MEM_STADDR1);
+       }
+       if (NAND_CS == 2) {
+               au_writel(NAND_STCFG,  MEM_STCFG2);
+               au_writel(NAND_STTIME, MEM_STTIME2);
+               au_writel(NAND_STADDR, MEM_STADDR2);
+       }
+       if (NAND_CS == 3) {
+               au_writel(NAND_STCFG,  MEM_STCFG3);
+               au_writel(NAND_STTIME, MEM_STTIME3);
+               au_writel(NAND_STADDR, MEM_STADDR3);
+       }
+#endif
+ 
+       /* Locate NAND chip-select in order to determine NAND phys address */
+       mem_staddr = 0x00000000;
+       if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
+               mem_staddr = au_readl(MEM_STADDR0);
+       else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
+               mem_staddr = au_readl(MEM_STADDR1);
+       else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
+               mem_staddr = au_readl(MEM_STADDR2);
+       else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
+               mem_staddr = au_readl(MEM_STADDR3);
+
+       if (mem_staddr == 0x00000000) {
+               printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
+               kfree(au1550_mtd);
+               return 1;
+       }
+       nand_phys = (mem_staddr << 4) & 0xFFFC0000;
+
+       p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
+
+       /* make controller and MTD agree */
+       if (NAND_CS == 0)
+               nand_width = au_readl(MEM_STCFG0) & (1<<22);
+       if (NAND_CS == 1)
+               nand_width = au_readl(MEM_STCFG1) & (1<<22);
+       if (NAND_CS == 2)
+               nand_width = au_readl(MEM_STCFG2) & (1<<22);
+       if (NAND_CS == 3)
+               nand_width = au_readl(MEM_STCFG3) & (1<<22);
 
-       p_nand = ioremap(NAND_PHYS_ADDR, 0x1000);
 
        /* Set address of hardware control function */
        this->hwcontrol = au1550_hwcontrol;
@@ -439,7 +462,7 @@
        }
 
        /* Register the partitions */
-       add_mtd_partitions(au1550_mtd, partition_info, NUM_PARTITIONS);
+       add_mtd_partitions(au1550_mtd, partition_info, NB_OF(partition_info));
 
        return 0;
 
@@ -451,7 +474,7 @@
        return retval;
 }
 
-module_init(au1550_init);
+module_init(au1xxx_nand_init);
 
 /*
  * Clean up routine
diff -urN linux/include/asm-mips/mach-db1x00/db1200.h 
linux/include/asm-mips/mach-db1x00/db1200.h
--- linux/include/asm-mips/mach-db1x00/db1200.h 2005/09/17 00:38:10     1.3
+++ linux/include/asm-mips/mach-db1x00/db1200.h 2005/09/23 01:47:41     1.4
@@ -220,5 +220,8 @@
 #define BOARD_PC1_INT DB1200_PC1_INT
 #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
 
+/* Nand chip select */
+#define NAND_CS 1
+
 #endif /* __ASM_DB1200_H */
 
diff -urN linux/include/asm-mips/mach-db1x00/db1x00.h 
linux/include/asm-mips/mach-db1x00/db1x00.h
--- linux/include/asm-mips/mach-db1x00/db1x00.h 2005/07/11 10:03:33     1.8
+++ linux/include/asm-mips/mach-db1x00/db1x00.h 2005/09/23 01:47:41     1.9
@@ -200,6 +200,12 @@
                        ((NAND_T_PUL & 0xF)     << NAND_T_PUL_SHIFT) | \
                        ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
                        ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
+#define NAND_CS 1
+
+/* should be done by yamon */
+#define NAND_STCFG  0x00400005 /* 8-bit NAND */
+#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
+#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
 
 #endif /* __ASM_DB1X00_H */
 
diff -urN linux/include/asm-mips/mach-pb1x00/pb1200.h 
linux/include/asm-mips/mach-pb1x00/pb1200.h
--- linux/include/asm-mips/mach-pb1x00/pb1200.h 2005/09/17 00:38:10     1.3
+++ linux/include/asm-mips/mach-pb1x00/pb1200.h 2005/09/23 01:47:41     1.4
@@ -248,5 +248,8 @@
 #define BOARD_PC1_INT PB1200_PC1_INT
 #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
 
+/* Nand chip select */
+#define NAND_CS 1
+
 #endif /* __ASM_PB1200_H */
 
diff -urN linux/include/asm-mips/mach-pb1x00/pb1550.h 
linux/include/asm-mips/mach-pb1x00/pb1550.h
--- linux/include/asm-mips/mach-pb1x00/pb1550.h 2005/01/18 05:21:55     1.4
+++ linux/include/asm-mips/mach-pb1x00/pb1550.h 2005/09/23 01:47:41     1.5
@@ -166,4 +166,11 @@
                        ((NAND_T_SU  & 0xF)     << NAND_T_SU_SHIFT)  | \
                        ((NAND_T_WH  & 0xF)     << NAND_T_WH_SHIFT)
 
+#define NAND_CS 1
+
+/* should be done by yamon */
+#define NAND_STCFG  0x00400005 /* 8-bit NAND */
+#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
+#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
+
 #endif /* __ASM_PB1550_H */

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