CVS Update@linux-mips.org: linux

[ths@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ths@ftp.linux-mips.org  05/09/02 13:18:30

Modified files:
        arch/mips/mm   : c-r4k.c pg-r4k.c 

Log message:
        Let r4600 PRID detection match only legacy CPUs.

diff -urN linux/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c
--- linux/arch/mips/mm/c-r4k.c  2005/09/02 09:56:12     1.116
+++ linux/arch/mips/mm/c-r4k.c  2005/09/02 12:18:30     1.117
@@ -50,8 +50,8 @@
 
 struct bcache_ops *bcops = &no_sc_ops;
 
-#define cpu_is_r4600_v1_x()    ((read_c0_prid() & 0xfff0) == 0x2010)
-#define cpu_is_r4600_v2_x()    ((read_c0_prid() & 0xfff0) == 0x2020)
+#define cpu_is_r4600_v1_x()    ((read_c0_prid() & 0xfffffff0) == 0x00002010)
+#define cpu_is_r4600_v2_x()    ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 
 #define R4600_HIT_CACHEOP_WAR_IMPL                                     \
 do {                                                                   \
diff -urN linux/arch/mips/mm/pg-r4k.c linux/arch/mips/mm/pg-r4k.c
--- linux/arch/mips/mm/pg-r4k.c 2005/09/01 18:33:58     1.18
+++ linux/arch/mips/mm/pg-r4k.c 2005/09/02 12:18:30     1.19
@@ -25,9 +25,9 @@
 #include <asm/cpu.h>
 #include <asm/war.h>
 
-#define half_scache_line_size()                (cpu_scache_line_size() >> 1)
-#define cpu_is_r4600_v1_x()            ((read_c0_prid() & 0xfff0) == 0x2010)
-#define cpu_is_r4600_v2_x()            ((read_c0_prid() & 0xfff0) == 0x2020)
+#define half_scache_line_size()        (cpu_scache_line_size() >> 1)
+#define cpu_is_r4600_v1_x()    ((read_c0_prid() & 0xfffffff0) == 0x00002010)
+#define cpu_is_r4600_v2_x()    ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 
 
 /*