CVS Update@linux-mips.org: linux

[ralf@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/08/16 17:26:33

Modified files:
        include/asm-mips: cpu-features.h 
        include/asm-mips: cpu.h 
        arch/mips/kernel: cpu-probe.c 

Log message:
        Rename MIPS_CPU_MIPSMT to MIPS_ASE_MIPSMT.

diff -urN linux/include/asm-mips/cpu-features.h 
linux/include/asm-mips/cpu-features.h
--- linux/include/asm-mips/cpu-features.h       2005/07/14 12:05:09     1.15
+++ linux/include/asm-mips/cpu-features.h       2005/08/16 16:26:32     1.16
@@ -127,7 +127,7 @@
 # endif
 #endif
 #ifndef cpu_has_mipsmt
-# define cpu_has_mipsmt                (cpu_data[0].ases & MIPS_CPU_MIPSMT)
+# define cpu_has_mipsmt                (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 #endif
 
 #ifdef CONFIG_64BIT
diff -urN linux/include/asm-mips/cpu.h linux/include/asm-mips/cpu.h
--- linux/include/asm-mips/cpu.h        2005/07/14 17:47:59     1.59
+++ linux/include/asm-mips/cpu.h        2005/08/16 16:26:32     1.60
@@ -231,7 +231,7 @@
 #define MIPS_CPU_PREFETCH      0x00040000 /* CPU has usable prefetch */
 #define MIPS_CPU_VINT          0x00080000 /* CPU supports MIPSR2 vectored 
interrupts */
 #define MIPS_CPU_VEIC          0x00100000 /* CPU supports MIPSR2 external 
interrupt controller mode */
-#define MIPS_CPU_MIPSMT                0x00400000 /* CPU supports MIPS MT */
+#define MIPS_ASE_MIPSMT                0x00400000 /* CPU supports MIPS MT */
 
 /*
  * CPU ASE encodings
diff -urN linux/arch/mips/kernel/cpu-probe.c linux/arch/mips/kernel/cpu-probe.c
--- linux/arch/mips/kernel/cpu-probe.c  2005/07/27 21:48:12     1.55
+++ linux/arch/mips/kernel/cpu-probe.c  2005/08/16 16:26:33     1.56
@@ -514,7 +514,7 @@
        if (config3 & MIPS_CONF3_VEIC)
                c->ases |= MIPS_CPU_VEIC;
        if (config3 & MIPS_CONF3_MT)
-                c->ases |= MIPS_CPU_MIPSMT;
+                c->ases |= MIPS_ASE_MIPSMT;
 
        return config3 & MIPS_CONF_M;
 }