CVS Update@linux-mips.org: linux

[ralf@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/08/16 16:44:07

Modified files:
        arch/mips/mips-boards/generic: init.c pci.c 
        arch/mips/mips-boards/malta: malta_int.c 
        include/asm-mips/mips-boards: generic.h 

Log message:
        Support for CoreFPGA-3.

diff -urN linux/arch/mips/mips-boards/generic/init.c 
linux/arch/mips/mips-boards/generic/init.c
--- linux/arch/mips/mips-boards/generic/init.c  2005/07/14 15:57:17     1.21
+++ linux/arch/mips/mips-boards/generic/init.c  2005/08/16 15:44:06     1.22
@@ -337,6 +337,7 @@
 
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
+       case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 
0x2000);
 
diff -urN linux/arch/mips/mips-boards/generic/pci.c 
linux/arch/mips/mips-boards/generic/pci.c
--- linux/arch/mips/mips-boards/generic/pci.c   2005/06/21 13:56:31     1.30
+++ linux/arch/mips/mips-boards/generic/pci.c   2005/08/16 15:44:06     1.31
@@ -197,6 +197,7 @@
 
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
+       case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                /* Set up resource ranges from the controller's registers.  */
                MSC_READ(MSC01_PCI_SC2PMBASL, start);
diff -urN linux/arch/mips/mips-boards/malta/malta_int.c 
linux/arch/mips/mips-boards/malta/malta_int.c
--- linux/arch/mips/mips-boards/malta/malta_int.c       2005/07/14 15:57:17     
1.27
+++ linux/arch/mips/mips-boards/malta/malta_int.c       2005/08/16 15:44:06     
1.28
@@ -57,6 +57,7 @@
        switch(mips_revision_corid) {
        case MIPS_REVISION_CORID_CORE_MSC:
        case MIPS_REVISION_CORID_CORE_FPGA2:
+       case MIPS_REVISION_CORID_CORE_FPGA3:
        case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                MSC_READ(MSC01_PCI_IACK, irq);
                irq &= 0xff;
@@ -103,22 +104,10 @@
        irq = mips_pcibios_iack();
 
        /*
-        * IRQ7 is used to detect spurious interrupts.
-        * The interrupt acknowledge cycle returns IRQ7, if no
-        * interrupts is requested.
-        * We can differentiate between this situation and a
-        * "Normal" IRQ7 by reading the ISR.
+        * The only way we can decide if an interrupt is spurious
+        * is by checking the 8259 registers.  This needs a spinlock
+        * on an SMP system,  so leave it up to the generic code...
         */
-       if (irq == 7)
-       {
-               outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
-                    PIIX4_ICTLR1_OCW3);
-               if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
-                       irq = -1; /* Spurious interrupt */
-                       printk("We got a spurious interrupt from PIIX4.\n");
-                       atomic_inc(&irq_err_count);
-               }
-       }
 
        spin_unlock_irqrestore(&mips_irq_lock, flags);
 
@@ -153,6 +142,7 @@
         switch(mips_revision_corid) {
         case MIPS_REVISION_CORID_CORE_MSC:
         case MIPS_REVISION_CORID_CORE_FPGA2:
+        case MIPS_REVISION_CORID_CORE_FPGA3:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                 ll_msc_irq(regs);
                 break;
@@ -233,6 +223,7 @@
         switch(mips_revision_corid) {
         case MIPS_REVISION_CORID_CORE_MSC:
         case MIPS_REVISION_CORID_CORE_FPGA2:
+        case MIPS_REVISION_CORID_CORE_FPGA3:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
                if (cpu_has_veic)
                        init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, 
msc_nr_eicirqs);
diff -urN linux/include/asm-mips/mips-boards/generic.h 
linux/include/asm-mips/mips-boards/generic.h
--- linux/include/asm-mips/mips-boards/generic.h        2005/06/21 13:56:32     
1.7
+++ linux/include/asm-mips/mips-boards/generic.h        2005/08/16 15:44:07     
1.8
@@ -66,6 +66,7 @@
 #define MIPS_REVISION_CORID_CORE_EMUL      6
 #define MIPS_REVISION_CORID_CORE_FPGA2     7
 #define MIPS_REVISION_CORID_CORE_FPGAR2    8
+#define MIPS_REVISION_CORID_CORE_FPGA3     9
 
 /**** Artificial corid defines ****/
 /*