CVS Update@linux-mips.org: linux

[ralf@linux-mips.org]

CVSROOT:        /home/cvs
Module name:    linux
Changes by:     ralf@ftp.linux-mips.org 05/08/12 17:57:46

Modified files:
        arch/mips/configs: tb0229_defconfig 
        arch/mips/pci  : fixup-tb0226.c 
        arch/mips/vr41xx: Kconfig 

Log message:
        Update GIU code for TB0226.

diff -urN linux/arch/mips/configs/tb0229_defconfig 
linux/arch/mips/configs/tb0229_defconfig
--- linux/arch/mips/configs/tb0229_defconfig    2005/08/12 16:46:27     1.74
+++ linux/arch/mips/configs/tb0229_defconfig    2005/08/12 16:57:46     1.75
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.13-rc6
-# Fri Aug 12 17:39:34 2005
+# Fri Aug 12 17:56:19 2005
 #
 CONFIG_MIPS=y
 
@@ -543,7 +543,7 @@
 # Ftape, the floppy tape device driver
 #
 # CONFIG_DRM is not set
-# CONFIG_GPIO_VR41XX is not set
+CONFIG_GPIO_VR41XX=y
 # CONFIG_RAW_DRIVER is not set
 
 #
diff -urN linux/arch/mips/pci/fixup-tb0226.c linux/arch/mips/pci/fixup-tb0226.c
--- linux/arch/mips/pci/fixup-tb0226.c  2004/10/31 16:07:33     1.9
+++ linux/arch/mips/pci/fixup-tb0226.c  2005/08/12 16:57:46     1.10
@@ -1,7 +1,7 @@
 /*
  *  fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups.
  *
- *  Copyright (C) 2002-2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ *  Copyright (C) 2002-2005  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 
+#include <asm/vr41xx/giu.h>
 #include <asm/vr41xx/tb0226.h>
 
 int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
@@ -29,42 +30,42 @@
        switch (slot) {
        case 12:
                vr41xx_set_irq_trigger(GD82559_1_PIN,
-                                      TRIGGER_LEVEL,
-                                      SIGNAL_THROUGH);
-               vr41xx_set_irq_level(GD82559_1_PIN, LEVEL_LOW);
+                                      IRQ_TRIGGER_LEVEL,
+                                      IRQ_SIGNAL_THROUGH);
+               vr41xx_set_irq_level(GD82559_1_PIN, IRQ_LEVEL_LOW);
                irq = GD82559_1_IRQ;
                break;
        case 13:
                vr41xx_set_irq_trigger(GD82559_2_PIN,
-                                      TRIGGER_LEVEL,
-                                      SIGNAL_THROUGH);
-               vr41xx_set_irq_level(GD82559_2_PIN, LEVEL_LOW);
+                                      IRQ_TRIGGER_LEVEL,
+                                      IRQ_SIGNAL_THROUGH);
+               vr41xx_set_irq_level(GD82559_2_PIN, IRQ_LEVEL_LOW);
                irq = GD82559_2_IRQ;
                break;
        case 14:
                switch (pin) {
                case 1:
                        vr41xx_set_irq_trigger(UPD720100_INTA_PIN,
-                                              TRIGGER_LEVEL,
-                                              SIGNAL_THROUGH);
+                                              IRQ_TRIGGER_LEVEL,
+                                              IRQ_SIGNAL_THROUGH);
                        vr41xx_set_irq_level(UPD720100_INTA_PIN,
-                                            LEVEL_LOW);
+                                            IRQ_LEVEL_LOW);
                        irq = UPD720100_INTA_IRQ;
                        break;
                case 2:
                        vr41xx_set_irq_trigger(UPD720100_INTB_PIN,
-                                              TRIGGER_LEVEL,
-                                              SIGNAL_THROUGH);
+                                              IRQ_TRIGGER_LEVEL,
+                                              IRQ_SIGNAL_THROUGH);
                        vr41xx_set_irq_level(UPD720100_INTB_PIN,
-                                            LEVEL_LOW);
+                                            IRQ_LEVEL_LOW);
                        irq = UPD720100_INTB_IRQ;
                        break;
                case 3:
                        vr41xx_set_irq_trigger(UPD720100_INTC_PIN,
-                                              TRIGGER_LEVEL,
-                                              SIGNAL_THROUGH);
+                                              IRQ_TRIGGER_LEVEL,
+                                              IRQ_SIGNAL_THROUGH);
                        vr41xx_set_irq_level(UPD720100_INTC_PIN,
-                                            LEVEL_LOW);
+                                            IRQ_LEVEL_LOW);
                        irq = UPD720100_INTC_IRQ;
                        break;
                default:
diff -urN linux/arch/mips/vr41xx/Kconfig linux/arch/mips/vr41xx/Kconfig
--- linux/arch/mips/vr41xx/Kconfig      2005/08/12 16:46:27     1.7
+++ linux/arch/mips/vr41xx/Kconfig      2005/08/12 16:57:46     1.8
@@ -58,6 +58,7 @@
        depends on TANBAC_TB022X
        select PCI
        select PCI_VR41XX
+       select GPIO_VR41XX
        help
          The TANBAC TB0226 (Mbase) is a MIPS-based platform manufactured by
          TANBAC.  Please refer to <http://www.tanbac.co.jp/> about Mbase.