CVSROOT: /home/cvs
Module name: linux
Changes by: ralf@ftp.linux-mips.org 05/07/27 00:22:44
Modified files:
drivers/net : sb1250-mac.c
Log message:
Get rid of all the funny SBMAC_WRITECSR and SBMAC_READCSR macros.
diff -urN linux/drivers/net/sb1250-mac.c linux/drivers/net/sb1250-mac.c
--- linux/drivers/net/sb1250-mac.c 2005/07/11 20:47:28 1.37
+++ linux/drivers/net/sb1250-mac.c 2005/07/26 23:22:44 1.38
@@ -467,15 +467,15 @@
uint64_t bits;
int mac_mdio_genc;
- mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
+ mac_mdio_genc = __raw_readq((unsigned long)s->sbm_mdio) & M_MAC_GENC;
bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
- SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
+ __raw_writeq(bits | mac_mdio_genc, (unsigned long)s->sbm_mdio);
for (cnt = 0; cnt < 32; cnt++) {
- SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
- SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
+ __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
+ __raw_writeq(bits | mac_mdio_genc, (unsigned long)s->sbm_mdio);
}
}
@@ -498,10 +498,10 @@
unsigned int curmask;
int mac_mdio_genc;
- mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
+ mac_mdio_genc = __raw_readq((unsigned long)s->sbm_mdio) & M_MAC_GENC;
bits = M_MAC_MDIO_DIR_OUTPUT;
- SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
+ __raw_writeq(bits | mac_mdio_genc, (unsigned long)s->sbm_mdio);
curmask = 1 << (bitcnt - 1);
@@ -509,9 +509,9 @@
if (data & curmask)
bits |= M_MAC_MDIO_OUT;
else bits &= ~M_MAC_MDIO_OUT;
- SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
- SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
- SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
+ __raw_writeq(bits | mac_mdio_genc, (unsigned long)s->sbm_mdio);
+ __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
+ __raw_writeq(bits | mac_mdio_genc, (unsigned long)s->sbm_mdio);
curmask >>= 1;
}
}
@@ -559,33 +559,31 @@
sbmac_mii_senddata(s,phyaddr, 5);
sbmac_mii_senddata(s,regidx, 5);
- mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
+ mac_mdio_genc = __raw_readq((unsigned long)s->sbm_mdio) & M_MAC_GENC;
/*
* Switch the port around without a clock transition.
*/
- SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
/*
* Send out a clock pulse to signal we want the status
*/
- SBMAC_WRITECSR(s->sbm_mdio,
- M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
- SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
(unsigned long)s->sbm_mdio);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
/*
* If an error occurred, the PHY will signal '1' back
*/
- error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
+ error = __raw_readq((unsigned long)s->sbm_mdio) & M_MAC_MDIO_IN;
/*
* Issue an 'idle' clock pulse, but keep the direction
* the same.
*/
- SBMAC_WRITECSR(s->sbm_mdio,
- M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
- SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
(unsigned long)s->sbm_mdio);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
regval = 0;
@@ -593,18 +591,16 @@
regval <<= 1;
if (error == 0) {
- if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN)
+ if (__raw_readq((unsigned long)s->sbm_mdio) &
M_MAC_MDIO_IN)
regval |= 1;
}
- SBMAC_WRITECSR(s->sbm_mdio,
- M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc);
- SBMAC_WRITECSR(s->sbm_mdio,
- M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc,
(unsigned long)s->sbm_mdio);
+ __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
}
/* Switch back to output */
- SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
+ __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
if (error == 0)
return regval;
@@ -641,9 +637,9 @@
sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
sbmac_mii_senddata(s,regval,16);
- mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
+ mac_mdio_genc = __raw_readq((unsigned long)s->sbm_mdio) & M_MAC_GENC;
- SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
+ __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, (unsigned
long)s->sbm_mdio);
}
@@ -685,48 +681,48 @@
s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
#endif
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
- SBMAC_WRITECSR(IOADDR(
- A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
+ __raw_writeq(0, (unsigned long)IOADDR(
+ A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
/*
* initialize register pointers
@@ -807,22 +803,19 @@
*/
#ifdef CONFIG_SBMAC_COALESCE
- SBMAC_WRITECSR(d->sbdma_config1,
- V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
- 0);
- SBMAC_WRITECSR(d->sbdma_config0,
- M_DMA_EOP_INT_EN |
+ __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
+ 0, (unsigned long)d->sbdma_config1);
+ __raw_writeq(M_DMA_EOP_INT_EN |
V_DMA_RINGSZ(d->sbdma_maxdescr) |
V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
- 0);
+ 0, (unsigned long)d->sbdma_config0);
#else
- SBMAC_WRITECSR(d->sbdma_config1,0);
- SBMAC_WRITECSR(d->sbdma_config0,
- V_DMA_RINGSZ(d->sbdma_maxdescr) |
- 0);
+ __raw_writeq(0, (unsigned long)d->sbdma_config1);
+ __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
+ 0, (unsigned long)d->sbdma_config0);
#endif
- SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
+ __raw_writeq(d->sbdma_dscrtable_phys, (unsigned long)d->sbdma_dscrbase);
/*
* Initialize ring pointers
@@ -850,11 +843,11 @@
* Turn off the DMA channel
*/
- SBMAC_WRITECSR(d->sbdma_config1,0);
+ __raw_writeq(0, (unsigned long)d->sbdma_config1);
- SBMAC_WRITECSR(d->sbdma_dscrbase,0);
+ __raw_writeq(0, (unsigned long)d->sbdma_dscrbase);
- SBMAC_WRITECSR(d->sbdma_config0,0);
+ __raw_writeq(0, (unsigned long)d->sbdma_config0);
/*
* Zero ring pointers
@@ -991,7 +984,7 @@
* Give the buffer to the DMA engine.
*/
- SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
+ __raw_writeq(1, (unsigned long)d->sbdma_dscrcnt);
return 0; /* we did it */
}
@@ -1081,7 +1074,7 @@
* Give the buffer to the DMA engine.
*/
- SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
+ __raw_writeq(1, (unsigned long)d->sbdma_dscrcnt);
return 0; /* we did it */
}
@@ -1177,7 +1170,7 @@
*/
curidx = d->sbdma_remptr - d->sbdma_dscrtable;
- hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) &
M_DMA_CURDSCR_ADDR) -
+ hwidx = (int) (((__raw_readq((unsigned long)d->sbdma_curdscr) &
M_DMA_CURDSCR_ADDR) -
d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
/*
@@ -1304,7 +1297,7 @@
*/
curidx = d->sbdma_remptr - d->sbdma_dscrtable;
- hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) &
M_DMA_CURDSCR_ADDR) -
+ hwidx = (int) (((__raw_readq((unsigned long)d->sbdma_curdscr) &
M_DMA_CURDSCR_ADDR) -
d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
/*
@@ -1475,13 +1468,13 @@
* Bring the controller out of reset, but leave it off.
*/
- SBMAC_WRITECSR(s->sbm_macenable,0);
+ __raw_writeq(0, (unsigned long)s->sbm_macenable);
/*
* Ignore all received packets
*/
- SBMAC_WRITECSR(s->sbm_rxfilter,0);
+ __raw_writeq(0, (unsigned long)s->sbm_rxfilter);
/*
* Calculate values for various control registers.
@@ -1525,7 +1518,7 @@
port = s->sbm_base + R_MAC_HASH_BASE;
for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
port += sizeof(uint64_t);
}
@@ -1535,7 +1528,7 @@
port = s->sbm_base + R_MAC_ADDR_BASE;
for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
port += sizeof(uint64_t);
}
@@ -1545,14 +1538,14 @@
port = s->sbm_base + R_MAC_CHUP0_BASE;
for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
port += sizeof(uint64_t);
}
port = s->sbm_base + R_MAC_CHLO0_BASE;
for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
port += sizeof(uint64_t);
}
@@ -1564,7 +1557,7 @@
reg = sbmac_addr2reg(s->sbm_hwaddr);
port = s->sbm_base + R_MAC_ADDR_BASE;
- SBMAC_WRITECSR(port,reg);
+ __raw_writeq(reg, (unsigned long)port);
port = s->sbm_base + R_MAC_ETHERNET_ADDR;
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
@@ -1573,9 +1566,9 @@
* destination address in the R_MAC_ETHERNET_ADDR register.
* Set the value to zero.
*/
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
#else
- SBMAC_WRITECSR(port,reg);
+ __raw_writeq(reg, (unsigned long)port);
#endif
/*
@@ -1583,11 +1576,11 @@
* to the various config registers
*/
- SBMAC_WRITECSR(s->sbm_rxfilter,0);
- SBMAC_WRITECSR(s->sbm_imr,0);
- SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
- SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
- SBMAC_WRITECSR(s->sbm_maccfg,cfg);
+ __raw_writeq(0, (unsigned long)s->sbm_rxfilter);
+ __raw_writeq(0, (unsigned long)s->sbm_imr);
+ __raw_writeq(framecfg, (unsigned long)s->sbm_framecfg);
+ __raw_writeq(fifo, (unsigned long)s->sbm_fifocfg);
+ __raw_writeq(cfg, (unsigned long)s->sbm_maccfg);
/*
* Initialize DMA channels (rings should be ok now)
@@ -1613,11 +1606,10 @@
* Turn on the rest of the bits in the enable register
*/
- SBMAC_WRITECSR(s->sbm_macenable,
- M_MAC_RXDMA_EN0 |
+ __raw_writeq(M_MAC_RXDMA_EN0 |
M_MAC_TXDMA_EN0 |
M_MAC_RX_ENABLE |
- M_MAC_TX_ENABLE);
+ M_MAC_TX_ENABLE, (unsigned long)s->sbm_macenable);
@@ -1626,23 +1618,21 @@
/*
* Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
*/
- SBMAC_WRITECSR(s->sbm_imr,
- ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) <<
S_MAC_TX_CH0) |
- ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) <<
S_MAC_RX_CH0));
+ __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) <<
S_MAC_TX_CH0) |
+ ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) <<
S_MAC_RX_CH0), (unsigned long)s->sbm_imr);
#else
/*
* Accept any kind of interrupt on TX and RX DMA channel 0
*/
- SBMAC_WRITECSR(s->sbm_imr,
- (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
- (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
+ __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
+ (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), (unsigned
long)s->sbm_imr);
#endif
/*
* Enable receiving unicasts and broadcasts
*/
- SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
+ __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, (unsigned
long)s->sbm_rxfilter);
/*
* we're running now.
@@ -1688,8 +1678,8 @@
/* don't accept any packets, disable all interrupts */
- SBMAC_WRITECSR(s->sbm_rxfilter,0);
- SBMAC_WRITECSR(s->sbm_imr,0);
+ __raw_writeq(0, (unsigned long)s->sbm_rxfilter);
+ __raw_writeq(0, (unsigned long)s->sbm_imr);
/* Turn off ticker */
@@ -1697,7 +1687,7 @@
/* turn off receiver and transmitter */
- SBMAC_WRITECSR(s->sbm_macenable,0);
+ __raw_writeq(0, (unsigned long)s->sbm_macenable);
/* We're stopped now. */
@@ -1781,14 +1771,14 @@
return;
if (onoff) {
- reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg = __raw_readq((unsigned long)sc->sbm_rxfilter);
reg |= M_MAC_ALLPKT_EN;
- SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+ __raw_writeq(reg, (unsigned long)sc->sbm_rxfilter);
}
else {
- reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg = __raw_readq((unsigned long)sc->sbm_rxfilter);
reg &= ~M_MAC_ALLPKT_EN;
- SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+ __raw_writeq(reg, (unsigned long)sc->sbm_rxfilter);
}
}
@@ -1809,9 +1799,9 @@
uint64_t reg;
/* Hard code the off set to 15 for now */
- reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg = __raw_readq((unsigned long)sc->sbm_rxfilter);
reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
- SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+ __raw_writeq(reg, (unsigned long)sc->sbm_rxfilter);
/* read system identification to determine revision */
if (periph_rev >= 2) {
@@ -1890,8 +1880,8 @@
* Read current register values
*/
- cfg = SBMAC_READCSR(s->sbm_maccfg);
- framecfg = SBMAC_READCSR(s->sbm_framecfg);
+ cfg = __raw_readq((unsigned long)s->sbm_maccfg);
+ framecfg = __raw_readq((unsigned long)s->sbm_framecfg);
/*
* Mask out the stuff we want to change
@@ -1940,8 +1930,8 @@
* Send the bits back to the hardware
*/
- SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
- SBMAC_WRITECSR(s->sbm_maccfg,cfg);
+ __raw_writeq(framecfg, (unsigned long)s->sbm_framecfg);
+ __raw_writeq(cfg, (unsigned long)s->sbm_maccfg);
return 1;
}
@@ -1980,7 +1970,7 @@
* Read current register values
*/
- cfg = SBMAC_READCSR(s->sbm_maccfg);
+ cfg = __raw_readq((unsigned long)s->sbm_maccfg);
/*
* Mask off the stuff we're about to change
@@ -2039,7 +2029,7 @@
* Send the bits back to the hardware
*/
- SBMAC_WRITECSR(s->sbm_maccfg,cfg);
+ __raw_writeq(cfg, (unsigned long)s->sbm_maccfg);
return 1;
}
@@ -2072,7 +2062,7 @@
* register, except for counter addr)
*/
- isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
+ isr = __raw_readq((unsigned long)sc->sbm_isr) &
~M_MAC_COUNTER_ADDR;
if (isr == 0)
break;
@@ -2186,30 +2176,30 @@
for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
}
for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
- SBMAC_WRITECSR(port,0);
+ __raw_writeq(0, (unsigned long)port);
}
/*
* Clear the filter to say we don't want any multicasts.
*/
- reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg = __raw_readq((unsigned long)sc->sbm_rxfilter);
reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
- SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+ __raw_writeq(reg, (unsigned long)sc->sbm_rxfilter);
if (dev->flags & IFF_ALLMULTI) {
/*
* Enable ALL multicasts. Do this by inverting the
* multicast enable bit.
*/
- reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg = __raw_readq((unsigned long)sc->sbm_rxfilter);
reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
- SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+ __raw_writeq(reg, (unsigned long)sc->sbm_rxfilter);
return;
}
@@ -2228,7 +2218,7 @@
while (mclist && (idx < MAC_ADDR_COUNT)) {
reg = sbmac_addr2reg(mclist->dmi_addr);
port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
- SBMAC_WRITECSR(port,reg);
+ __raw_writeq(reg, (unsigned long)port);
idx++;
mclist = mclist->next;
}
@@ -2239,9 +2229,9 @@
*/
if (idx > 1) {
- reg = SBMAC_READCSR(sc->sbm_rxfilter);
+ reg = __raw_readq((unsigned long)sc->sbm_rxfilter);
reg |= M_MAC_MCAST_EN;
- SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
+ __raw_writeq(reg, (unsigned long)sc->sbm_rxfilter);
}
}
@@ -2370,8 +2360,8 @@
* for us in the ethernet address register for each mac.
*/
- ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR);
- SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0);
+ ea_reg = __raw_readq((unsigned long)sc->sbm_base + R_MAC_ETHERNET_ADDR);
+ __raw_writeq(0, (unsigned long)sc->sbm_base + R_MAC_ETHERNET_ADDR);
for (i = 0; i < 6; i++) {
eaddr[i] = (uint8_t) (ea_reg & 0xFF);
ea_reg >>= 8;
@@ -2463,7 +2453,7 @@
* yet)
*/
- SBMAC_READCSR(sc->sbm_isr);
+ __raw_readq((unsigned long)sc->sbm_isr);
if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
return -EBUSY;
@@ -2803,8 +2793,8 @@
port = A_MAC_CHANNEL_BASE(chan);
sbmac_parse_hwaddr(addr,eaddr);
val = sbmac_addr2reg(eaddr);
- SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),val);
- val = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
+ __raw_writeq(val, (unsigned long)IOADDR(port+R_MAC_ETHERNET_ADDR));
+ val = __raw_readq((unsigned long)IOADDR(port+R_MAC_ETHERNET_ADDR));
}
#endif
@@ -2869,7 +2859,7 @@
* If we find a zero, skip this MAC.
*/
- sbmac_orig_hwaddr[idx] =
SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
+ sbmac_orig_hwaddr[idx] = __raw_readq((unsigned
long)IOADDR(port+R_MAC_ETHERNET_ADDR));
if (sbmac_orig_hwaddr[idx] == 0) {
printk(KERN_DEBUG "sbmac: not configuring MAC at "
"%lx\n", port);
@@ -2891,8 +2881,7 @@
dev->mem_end = 0;
if (sbmac_init(dev, idx)) {
port = A_MAC_CHANNEL_BASE(idx);
- SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),
- sbmac_orig_hwaddr[idx]);
+ __raw_writeq(sbmac_orig_hwaddr[idx], (unsigned
long)IOADDR(port+R_MAC_ETHERNET_ADDR));
free_netdev(dev);
continue;
}
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