CVSROOT: /home/cvs
Module name: linux
Changes by: ralf@ftp.linux-mips.org 05/07/25 22:36:00
Modified files:
include/asm-mips/mach-generic: kernel-entry-init.h
include/asm-mips/mach-ip27: kernel-entry-init.h
include/asm-mips/mach-pnx8550: glb.h kernel-entry-init.h nand.h
pci.h usb.h
arch/mips/au1000/common: irq.c
arch/mips/pci : ops-pnx8550.c
arch/mips/philips/pnx8550/common: gdb_hook.c int.c pci.c proc.c
prom.c setup.c
arch/mips/philips/pnx8550/jbs: board_setup.c init.c
Log message:
Fixup the trailing whitespace mess.
diff -urN linux/include/asm-mips/mach-generic/kernel-entry-init.h
linux/include/asm-mips/mach-generic/kernel-entry-init.h
--- linux/include/asm-mips/mach-generic/kernel-entry-init.h 2005/07/14
09:42:34 1.1
+++ linux/include/asm-mips/mach-generic/kernel-entry-init.h 2005/07/25
21:35:59 1.2
@@ -8,7 +8,7 @@
#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
-/* Intentionally empty macro, used in head.S. Override in
+/* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/
.macro kernel_entry_setup
diff -urN linux/include/asm-mips/mach-ip27/kernel-entry-init.h
linux/include/asm-mips/mach-ip27/kernel-entry-init.h
--- linux/include/asm-mips/mach-ip27/kernel-entry-init.h 2005/07/14
09:42:34 1.1
+++ linux/include/asm-mips/mach-ip27/kernel-entry-init.h 2005/07/25
21:35:59 1.2
@@ -24,7 +24,7 @@
.endm
/*
- * Intentionally empty macro, used in head.S. Override in
+ * Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/
.macro kernel_entry_setup
diff -urN linux/include/asm-mips/mach-pnx8550/glb.h
linux/include/asm-mips/mach-pnx8550/glb.h
--- linux/include/asm-mips/mach-pnx8550/glb.h 2005/07/14 17:47:59 1.1
+++ linux/include/asm-mips/mach-pnx8550/glb.h 2005/07/25 21:35:59 1.2
@@ -31,13 +31,13 @@
/* PCI Inta Output Enable Registers */
#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long
*)(PNX8550_GLB2_BASE + 0x050)
-/* Bit 1:Enable DAC Powerdown
- 0:DACs are enabled and are working normally
+/* Bit 1:Enable DAC Powerdown
+ 0:DACs are enabled and are working normally
1:DACs are powerdown
*/
#define PNX8550_GLB_DAC_PD 0x2
-/* Bit 0:Enable of PCI inta output
- 0 = Disable PCI inta output
+/* Bit 0:Enable of PCI inta output
+ 0 = Disable PCI inta output
1 = Enable PCI inta output
*/
#define PNX8550_GLB_ENABLE_INTA_O 0x1
diff -urN linux/include/asm-mips/mach-pnx8550/kernel-entry-init.h
linux/include/asm-mips/mach-pnx8550/kernel-entry-init.h
--- linux/include/asm-mips/mach-pnx8550/kernel-entry-init.h 2005/07/14
17:47:59 1.1
+++ linux/include/asm-mips/mach-pnx8550/kernel-entry-init.h 2005/07/25
21:35:59 1.2
@@ -79,7 +79,7 @@
/* enable TLB. */
mtc0 t0, CP0_CONFIG, 7
HAZARD_CP0
-cache_end:
+cache_end:
/* Setup CMEM_0 to MMIO address space, 2MB */
lui t0, 0x1BE0
addi t0, t0, 0x3
@@ -91,7 +91,7 @@
addi t0, t0, 0xf
mtc0 $8, $22, 5
nop
-
+
/* Setup CMEM_2, 32MB */
lui t0, 0x1C00
@@ -111,7 +111,7 @@
and t0, t0, 0xFFFFFFF8
or t0, t0, 3
mtc0 t0, CP0_CONFIG
- HAZARD_CP0
+ HAZARD_CP0
.set pop
.endm
diff -urN linux/include/asm-mips/mach-pnx8550/nand.h
linux/include/asm-mips/mach-pnx8550/nand.h
--- linux/include/asm-mips/mach-pnx8550/nand.h 2005/07/14 17:47:59 1.1
+++ linux/include/asm-mips/mach-pnx8550/nand.h 2005/07/25 21:35:59 1.2
@@ -94,28 +94,28 @@
#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
-#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
-#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
+#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
+#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
-#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
-#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
-#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
-#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
+#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
+#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
+#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
+#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
-#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
-#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
+#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
+#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
-#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
-#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
-#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
-#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
+#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
+#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
+#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
+#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
-#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
-#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
+#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
+#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
-#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
-#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
-#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
-#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
+#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
+#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
+#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
+#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
#endif
diff -urN linux/include/asm-mips/mach-pnx8550/pci.h
linux/include/asm-mips/mach-pnx8550/pci.h
--- linux/include/asm-mips/mach-pnx8550/pci.h 2005/07/14 17:47:59 1.1
+++ linux/include/asm-mips/mach-pnx8550/pci.h 2005/07/25 21:35:59 1.2
@@ -1,7 +1,7 @@
/*
*
* BRIEF MODULE DESCRIPTION
- * PCI specific definitions
+ * PCI specific definitions
*
* Author: source@mvista.com
*
diff -urN linux/include/asm-mips/mach-pnx8550/usb.h
linux/include/asm-mips/mach-pnx8550/usb.h
--- linux/include/asm-mips/mach-pnx8550/usb.h 2005/07/14 17:47:59 1.1
+++ linux/include/asm-mips/mach-pnx8550/usb.h 2005/07/25 21:35:59 1.2
@@ -1,7 +1,7 @@
/*
*
* BRIEF MODULE DESCRIPTION
- * USB specific definitions
+ * USB specific definitions
*
* Author: source@mvista.com
*
diff -urN linux/arch/mips/au1000/common/irq.c
linux/arch/mips/au1000/common/irq.c
--- linux/arch/mips/au1000/common/irq.c 2005/07/19 07:05:36 1.41
+++ linux/arch/mips/au1000/common/irq.c 2005/07/25 21:36:00 1.42
@@ -300,13 +300,13 @@
static struct irqaction action;
memset(&action, 0, sizeof(struct irqaction));
- /* This is a big problem.... since we didn't use request_irq
- * when kernel/irq.c calls probe_irq_xxx this interrupt will
- * be probed for usage. This will end up disabling the device :(
- * Give it a bogus "action" pointer -- this will keep it from
- * getting auto-probed!
+ /* This is a big problem.... since we didn't use request_irq
+ * when kernel/irq.c calls probe_irq_xxx this interrupt will
+ * be probed for usage. This will end up disabling the device :(
+ * Give it a bogus "action" pointer -- this will keep it from
+ * getting auto-probed!
*
- * By setting the status to match that of request_irq() we
+ * By setting the status to match that of request_irq() we
* can avoid it. --cgray
*/
action.dev_id = handler;
@@ -316,7 +316,7 @@
action.handler = handler;
action.next = NULL;
- desc->action = &action;
+ desc->action = &action;
desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING |
IRQ_INPROGRESS);
local_enable_irq(AU1000_TOY_MATCH2_INT);
diff -urN linux/arch/mips/pci/ops-pnx8550.c linux/arch/mips/pci/ops-pnx8550.c
--- linux/arch/mips/pci/ops-pnx8550.c 2005/07/14 17:47:58 1.1
+++ linux/arch/mips/pci/ops-pnx8550.c 2005/07/25 21:36:00 1.2
@@ -1,7 +1,7 @@
/*
*
* BRIEF MODULE DESCRIPTION
- *
+ *
* 2.6 port, Embedded Alley Solutions, Inc
*
* Based on:
diff -urN linux/arch/mips/philips/pnx8550/common/gdb_hook.c
linux/arch/mips/philips/pnx8550/common/gdb_hook.c
--- linux/arch/mips/philips/pnx8550/common/gdb_hook.c 2005/07/14 17:47:58
1.1
+++ linux/arch/mips/philips/pnx8550/common/gdb_hook.c 2005/07/25 21:36:00
1.2
@@ -69,7 +69,7 @@
/* Clear all the receiver FIFO counters (pointer and status) */
PNX8550_UART_LCR(tty_no) |= PNX8550_UART_LCR_RX_RST;
/* Clear all interrupts */
- PNX8550_UART_ICLR(tty_no) = PNX8550_UART_INT_ALLRX |
+ PNX8550_UART_ICLR(tty_no) = PNX8550_UART_INT_ALLRX |
PNX8550_UART_INT_ALLTX;
/*
@@ -82,7 +82,7 @@
int putDebugChar(char c)
{
/* Wait until FIFO not full */
- while (((PNX8550_UART_FIFO(kdb_port_info.port) &
PNX8550_UART_FIFO_TXFIFO) >> 16) >= 16)
+ while (((PNX8550_UART_FIFO(kdb_port_info.port) &
PNX8550_UART_FIFO_TXFIFO) >> 16) >= 16)
;
/* Send one char */
PNX8550_UART_FIFO(kdb_port_info.port) = c;
@@ -95,8 +95,8 @@
char ch;
/* Wait until there is a char in the FIFO */
- while (!((PNX8550_UART_FIFO(kdb_port_info.port) &
- PNX8550_UART_FIFO_RXFIFO) >> 8))
+ while (!((PNX8550_UART_FIFO(kdb_port_info.port) &
+ PNX8550_UART_FIFO_RXFIFO) >> 8))
;
/* Read one char */
ch = PNX8550_UART_FIFO(kdb_port_info.port) & PNX8550_UART_FIFO_RBRTHR;
@@ -117,7 +117,7 @@
/* Clear all the receiver FIFO counters (pointer and status) */
PNX8550_UART_LCR(kdb_port_info.port) |= PNX8550_UART_LCR_RX_RST;
/* Clear all interrupts */
- PNX8550_UART_ICLR(kdb_port_info.port) = PNX8550_UART_INT_ALLRX |
+ PNX8550_UART_ICLR(kdb_port_info.port) = PNX8550_UART_INT_ALLRX |
PNX8550_UART_INT_ALLTX;
PNX8550_UART_IEN(kdb_port_info.port) = PNX8550_UART_INT_ALLRX; /*
Enable RX interrupts */
}
diff -urN linux/arch/mips/philips/pnx8550/common/int.c
linux/arch/mips/philips/pnx8550/common/int.c
--- linux/arch/mips/philips/pnx8550/common/int.c 2005/07/14 17:47:58
1.1
+++ linux/arch/mips/philips/pnx8550/common/int.c 2005/07/25 21:36:00
1.2
@@ -8,7 +8,7 @@
* Copyright (C) 2001 Ralf Baechle
*
* Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
- *
+ *
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
@@ -114,10 +114,10 @@
{
if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX))
{
modify_cp0_intmask(1 << irq_nr, 0);
- } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
- (irq_nr <= PNX8550_INT_GIC_MAX)) {
+ } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
+ (irq_nr <= PNX8550_INT_GIC_MAX)) {
mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
- } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
+ } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_TIMER_MAX)) {
modify_cp0_intmask(1 << 7, 0);
} else {
@@ -129,10 +129,10 @@
{
if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX))
{
modify_cp0_intmask(0, 1 << irq_nr);
- } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
+ } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_GIC_MAX)) {
unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
- } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
+ } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
(irq_nr <= PNX8550_INT_TIMER_MAX)) {
modify_cp0_intmask(0, 1 << 7);
} else {
@@ -237,11 +237,11 @@
int gic_int_line = i - PNX8550_INT_GIC_MIN;
if (gic_int_line == 0 )
continue; // don't fiddle with int 0
- /*
+ /*
* enable change of TARGET, ENABLE and ACTIVE_LOW bits
* set TARGET 0 to route through hw0 interrupt
* set ACTIVE_LOW 0 active high (correct?)
- *
+ *
* We really should setup an interrupt description table
* to do this nicely.
* Note, PCI INTA is active low on the bus, but inverted
@@ -249,19 +249,19 @@
*/
#ifdef CONFIG_PNX8550_V2PCI
if (gic_int_line == (PNX8550_INT_GPIO0 - PNX8550_INT_GIC_MIN)) {
- /* PCI INT through gpio 8, which is setup in
+ /* PCI INT through gpio 8, which is setup in
* pnx8550_setup.c and routed to GPIO
* Interrupt Level 0 (GPIO Connection 58).
* Set it active low. */
-
+
PNX8550_GIC_REQ(gic_int_line) = 0x1E020000;
- } else
+ } else
#endif
{
PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
}
- /* mask/priority is still 0 so we will not get any
+ /* mask/priority is still 0 so we will not get any
* interrupts until it is unmasked */
irq_desc[i].handler = &level_irq_type;
diff -urN linux/arch/mips/philips/pnx8550/common/pci.c
linux/arch/mips/philips/pnx8550/common/pci.c
--- linux/arch/mips/philips/pnx8550/common/pci.c 2005/07/14 17:47:58
1.1
+++ linux/arch/mips/philips/pnx8550/common/pci.c 2005/07/25 21:36:00
1.2
@@ -54,9 +54,9 @@
static inline unsigned long get_system_mem_size(void)
{
/* Read IP2031_RANK0_ADDR_LO */
- unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+ unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
/* Read IP2031_RANK1_ADDR_HI */
- unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+ unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
return dram_r1_hi - dram_r0_lo + 1;
}
@@ -67,11 +67,11 @@
int mem_size = get_system_mem_size() >> 20;
/* Clear the Global 2 Register, PCI Inta Output Enable Registers
- Bit 1:Enable DAC Powerdown
- -> 0:DACs are enabled and are working normally
+ Bit 1:Enable DAC Powerdown
+ -> 0:DACs are enabled and are working normally
1:DACs are powerdown
- Bit 0:Enable of PCI inta output
- -> 0 = Disable PCI inta output
+ Bit 0:Enable of PCI inta output
+ -> 0 = Disable PCI inta output
1 = Enable PCI inta output
*/
PNX8550_GLB2_ENAB_INTA_O = 0;
@@ -98,14 +98,14 @@
/* Unlock the setup register */
outl(0xca, PCI_BASE | PCI_UNLOCKREG);
- /*
+ /*
* BAR0 of PNX8550 (pci base 10) must be zero in order for ide
- * to work, and in order for bus_to_baddr to work without any
+ * to work, and in order for bus_to_baddr to work without any
* hacks.
*/
outl(0x00000000, PCI_BASE | PCI_BASE10);
- /*
+ /*
*These two bars are set by default or the boot code.
* However, it's safer to set them here so we're not boot
* code dependent.
@@ -113,17 +113,17 @@
outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
- outl(PCI_EN_TA |
- PCI_EN_PCI2MMI |
- PCI_EN_XIO |
- PCI_SETUP_BASE18_SIZE(SIZE_32M) |
- PCI_SETUP_BASE18_EN |
- PCI_SETUP_BASE14_EN |
- PCI_SETUP_BASE10_PREF |
- PCI_SETUP_BASE10_SIZE(pci_mem_code) |
+ outl(PCI_EN_TA |
+ PCI_EN_PCI2MMI |
+ PCI_EN_XIO |
+ PCI_SETUP_BASE18_SIZE(SIZE_32M) |
+ PCI_SETUP_BASE18_EN |
+ PCI_SETUP_BASE14_EN |
+ PCI_SETUP_BASE10_PREF |
+ PCI_SETUP_BASE10_SIZE(pci_mem_code) |
PCI_SETUP_CFGMANAGE_EN |
PCI_SETUP_PCIARB_EN,
- PCI_BASE |
+ PCI_BASE |
PCI_SETUP); /* PCI_SETUP */
outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
diff -urN linux/arch/mips/philips/pnx8550/common/proc.c
linux/arch/mips/philips/pnx8550/common/proc.c
--- linux/arch/mips/philips/pnx8550/common/proc.c 2005/07/14 17:47:58
1.1
+++ linux/arch/mips/philips/pnx8550/common/proc.c 2005/07/25 21:36:00
1.2
@@ -36,16 +36,16 @@
if (offset==0) {
len += sprintf(&page[len],"Timer: count, compare, tc,
status\n");
len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n",
- read_c0_count(), read_c0_compare(),
+ read_c0_count(), read_c0_compare(),
(configPR>>6)&0x1, ((configPR>>3)&0x1)?
"off":"on");
len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n",
- read_c0_count2(), read_c0_compare2(),
+ read_c0_count2(), read_c0_compare2(),
(configPR>>7)&0x1, ((configPR>>4)&0x1)?
"off":"on");
len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n",
- read_c0_count3(), read_c0_compare3(),
+ read_c0_count3(), read_c0_compare3(),
(configPR>>8)&0x1, ((configPR>>5)&0x1)?
"off":"on");
}
-
+
return len;
}
@@ -59,7 +59,7 @@
len += sprintf(&page[len],"config3:
%#10.8x\n",read_c0_config3());
len += sprintf(&page[len],"configPR:
%#10.8x\n",read_c0_config7());
len += sprintf(&page[len],"status:
%#10.8x\n",read_c0_status());
- len += sprintf(&page[len],"cause:
%#10.8x\n",read_c0_cause());
+ len += sprintf(&page[len],"cause:
%#10.8x\n",read_c0_cause());
len += sprintf(&page[len],"count:
%#10.8x\n",read_c0_count());
len += sprintf(&page[len],"count_2:
%#10.8x\n",read_c0_count2());
len += sprintf(&page[len],"count_3:
%#10.8x\n",read_c0_count3());
@@ -67,7 +67,7 @@
len += sprintf(&page[len],"compare_2:
%#10.8x\n",read_c0_compare2());
len += sprintf(&page[len],"compare_3:
%#10.8x\n",read_c0_compare3());
}
-
+
return len;
}
@@ -77,7 +77,7 @@
static int pnx8550_proc_init( void )
{
-
+
// Create /proc/pnx8550
pnx8550_dir = create_proc_entry("pnx8550", S_IFDIR|S_IRUGO, NULL);
if (pnx8550_dir){
@@ -89,7 +89,7 @@
}
// Create /proc/pnx8550/timers
- pnx8550_timers = create_proc_entry("timers", S_IFREG|S_IRUGO,
pnx8550_dir );
+ pnx8550_timers = create_proc_entry("timers", S_IFREG|S_IRUGO,
pnx8550_dir );
if (pnx8550_timers){
pnx8550_timers->nlink = 1;
pnx8550_timers->read_proc = pnx8550_timers_read;
@@ -99,7 +99,7 @@
}
// Create /proc/pnx8550/registers
- pnx8550_registers = create_proc_entry("registers", S_IFREG|S_IRUGO,
pnx8550_dir );
+ pnx8550_registers = create_proc_entry("registers", S_IFREG|S_IRUGO,
pnx8550_dir );
if (pnx8550_registers){
pnx8550_registers->nlink = 1;
pnx8550_registers->read_proc = pnx8550_registers_read;
@@ -107,7 +107,7 @@
else {
printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
}
-
+
return 0;
}
diff -urN linux/arch/mips/philips/pnx8550/common/prom.c
linux/arch/mips/philips/pnx8550/common/prom.c
--- linux/arch/mips/philips/pnx8550/common/prom.c 2005/07/14 17:47:58
1.1
+++ linux/arch/mips/philips/pnx8550/common/prom.c 2005/07/25 21:36:00
1.2
@@ -121,7 +121,7 @@
void prom_putchar(char c)
{
/* Wait until FIFO not full */
- while( ((PNX8550_UART_FIFO(PNX8550_CONSOLE_PORT)
+ while( ((PNX8550_UART_FIFO(PNX8550_CONSOLE_PORT)
& PNX8550_UART_FIFO_TXFIFO) >> 16) >= 16)
;
/* Send one char */
diff -urN linux/arch/mips/philips/pnx8550/common/setup.c
linux/arch/mips/philips/pnx8550/common/setup.c
--- linux/arch/mips/philips/pnx8550/common/setup.c 2005/07/14 17:47:58
1.1
+++ linux/arch/mips/philips/pnx8550/common/setup.c 2005/07/25 21:36:00
1.2
@@ -75,9 +75,9 @@
unsigned long get_system_mem_size(void)
{
/* Read IP2031_RANK0_ADDR_LO */
- unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+ unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
/* Read IP2031_RANK1_ADDR_HI */
- unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+ unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
return dram_r1_hi - dram_r0_lo + 1;
}
@@ -97,11 +97,11 @@
board_timer_setup = pnx8550_timer_setup;
/* Clear the Global 2 Register, PCI Inta Output Enable Registers
- Bit 1:Enable DAC Powerdown
- -> 0:DACs are enabled and are working normally
+ Bit 1:Enable DAC Powerdown
+ -> 0:DACs are enabled and are working normally
1:DACs are powerdown
- Bit 0:Enable of PCI inta output
- -> 0 = Disable PCI inta output
+ Bit 0:Enable of PCI inta output
+ -> 0 = Disable PCI inta output
1 = Enable PCI inta output
*/
PNX8550_GLB2_ENAB_INTA_O = 0;
@@ -119,8 +119,8 @@
/* Place the Mode Control bit for GPIO pin 16 in primary function */
/* Pin 16 is used by UART1, UA1_TX */
- outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
- (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
+ outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
+ (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
PNX8550_GPIO_MC1);
argptr = prom_getcmdline();
diff -urN linux/arch/mips/philips/pnx8550/jbs/board_setup.c
linux/arch/mips/philips/pnx8550/jbs/board_setup.c
--- linux/arch/mips/philips/pnx8550/jbs/board_setup.c 2005/07/14 17:47:59
1.1
+++ linux/arch/mips/philips/pnx8550/jbs/board_setup.c 2005/07/25 21:36:00
1.2
@@ -54,11 +54,11 @@
/* clear all three cache coherency fields */
config0 &= ~(0x7 | (7<<25) | (7<<28));
- config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
+ config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
(CONF_CM_DEFAULT<<28));
write_c0_config(config0);
BARRIER;
-
+
configpr = read_c0_config7();
configpr |= (1<<19); /* enable tlb */
write_c0_config7(configpr);
diff -urN linux/arch/mips/philips/pnx8550/jbs/init.c
linux/arch/mips/philips/pnx8550/jbs/init.c
--- linux/arch/mips/philips/pnx8550/jbs/init.c 2005/07/14 17:47:59 1.1
+++ linux/arch/mips/philips/pnx8550/jbs/init.c 2005/07/25 21:36:00 1.2
@@ -1,5 +1,5 @@
/*
- *
+ *
* Copyright 2005 Embedded Alley Solutions, Inc
* source@embeddedalley.com
*
@@ -46,7 +46,7 @@
void __init prom_init(void)
{
-
+
unsigned long memsize;
mips_machgroup = MACH_GROUP_PHILIPS;
|